mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 04:02:41 +01:00
2911459942
Minor bugfixing and improvements. See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 350120
111 lines
3.5 KiB
ReStructuredText
111 lines
3.5 KiB
ReStructuredText
============================
|
|
AMDGPU Instructions Notation
|
|
============================
|
|
|
|
.. contents::
|
|
:local:
|
|
|
|
.. _amdgpu_syn_instruction_notation:
|
|
|
|
Introduction
|
|
============
|
|
|
|
This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
|
|
|
|
This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
|
|
except that instead of real operands and modifiers it provides references to their description.
|
|
|
|
Instructions
|
|
============
|
|
|
|
Notation
|
|
~~~~~~~~
|
|
|
|
This is the notation used to describe AMDGPU instructions:
|
|
|
|
``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``> <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``> <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
|
|
|
|
.. _amdgpu_syn_opcode_notation:
|
|
|
|
Opcode
|
|
======
|
|
|
|
Notation
|
|
~~~~~~~~
|
|
|
|
TBD
|
|
|
|
.. _amdgpu_syn_instruction_operands_notation:
|
|
|
|
Operands
|
|
========
|
|
|
|
An instruction may have zero or more *operands*. They are comma-separated in the description:
|
|
|
|
``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>, <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
|
|
|
|
The order of *operands* is fixed. *Operands* cannot be omitted
|
|
except for special cases described below.
|
|
|
|
.. _amdgpu_syn_instruction_operand_notation:
|
|
|
|
Notation
|
|
~~~~~~~~
|
|
|
|
An operand is described using the following notation:
|
|
|
|
*<name><tag0><tag1>...*
|
|
|
|
Where:
|
|
|
|
* *name* is a link to a description of the operand.
|
|
* *tags* are optional. They are used to indicate special operand properties:
|
|
|
|
.. _amdgpu_syn_instruction_operand_tags:
|
|
|
|
============== =================================================================================
|
|
Operand tag Meaning
|
|
============== =================================================================================
|
|
:opt An optional operand.
|
|
:m An operand which may be used with
|
|
:ref:`VOP3 operand modifiers<amdgpu_synid_vop3_operand_modifiers>` or
|
|
:ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
|
|
:dst An input operand which may also serve as a destination
|
|
if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
|
|
:fx This is an *f32* or *f16* operand depending on
|
|
:ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
|
|
:<type> Operand *type* differs from *type*
|
|
:ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
|
|
This tag specifies actual operand *type*.
|
|
============== =================================================================================
|
|
|
|
Examples:
|
|
|
|
.. parsed-literal::
|
|
|
|
src1:m // src1 operand may be used with operand modifiers
|
|
vdata:dst // vdata operand may be used as both source and destination
|
|
vdst:u32 // vdst operand has u32 type
|
|
|
|
.. _amdgpu_syn_instruction_modifiers_notation:
|
|
|
|
Modifiers
|
|
=========
|
|
|
|
An instruction may have zero or more optional *modifiers*. They are space-separated in the description:
|
|
|
|
``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``> <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
|
|
|
|
The order of *modifiers* is fixed.
|
|
|
|
.. _amdgpu_syn_instruction_modifier_notation:
|
|
|
|
Notation
|
|
~~~~~~~~
|
|
|
|
A *modifier* is described using the following notation:
|
|
|
|
*<name>*
|
|
|
|
Where *name* is a link to a description of the *modifier*.
|