1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/Hexagon/bug15515-shuffle.ll
Krzysztof Parzyszek 66abdd815e [Hexagon] Add more lit tests
llvm-svn: 327271
2018-03-12 14:01:28 +00:00

46 lines
1.3 KiB
LLVM

; RUN: opt -march=hexagon -O2 -vectorize-loops -S < %s
; REQUIRES: asserts
;
; -fvectorize-loops infinite compile/memory
; test checks that the compile completes successfully
target triple = "hexagon"
@g0 = global i8 -1, align 1
@g1 = common global [15 x i8] zeroinitializer, align 8
@g2 = common global [15 x i8*] zeroinitializer, align 8
; Function Attrs: nounwind
define void @f0() #0 {
b0:
%v0 = alloca i32, align 4
store i32 0, i32* %v0, align 4
store i32 0, i32* %v0, align 4
br label %b1
b1: ; preds = %b3, %b0
%v1 = load i32, i32* %v0, align 4
%v2 = icmp slt i32 %v1, 15
br i1 %v2, label %b2, label %b4
b2: ; preds = %b1
%v3 = load i32, i32* %v0, align 4
%v4 = getelementptr inbounds [15 x i8], [15 x i8]* @g1, i32 0, i32 %v3
store i8 0, i8* %v4, align 1
%v5 = load i32, i32* %v0, align 4
%v6 = getelementptr inbounds [15 x i8*], [15 x i8*]* @g2, i32 0, i32 %v5
store i8* @g0, i8** %v6, align 4
br label %b3
b3: ; preds = %b2
%v7 = load i32, i32* %v0, align 4
%v8 = add nsw i32 %v7, 1
store i32 %v8, i32* %v0, align 4
br label %b1
b4: ; preds = %b1
ret void
}
attributes #0 = { nounwind }