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91ee3c678b
(op ... (zext i1 c) ...) -> (select c (op ... 1 ...), (op ... 0 ...)) llvm-svn: 297391
14 lines
446 B
LLVM
14 lines
446 B
LLVM
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
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; In the IR, the i1 value is zero-extended first, then passed to add.
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; Check that in the final code, the mux happens after the add.
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; CHECK: [[REG1:r[0-9]+]] = add([[REG0:r[0-9]+]],#1)
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; CHECK: r{{[0-9]+}} = mux(p{{[0-3]}},[[REG1]],[[REG0]])
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define i32 @foo(i32 %a, i32 %b) {
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%v0 = icmp eq i32 %a, %b
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%v1 = zext i1 %v0 to i32
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%v2 = add i32 %v1, %a
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ret i32 %v2
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}
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