1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
llvm-mirror/test/CodeGen/Hexagon/isel-op-zext-i1.ll
Krzysztof Parzyszek 91ee3c678b [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG
(op ... (zext i1 c) ...) -> (select c (op ... 1 ...),
                                      (op ... 0 ...))

llvm-svn: 297391
2017-03-09 16:29:30 +00:00

14 lines
446 B
LLVM

; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
; In the IR, the i1 value is zero-extended first, then passed to add.
; Check that in the final code, the mux happens after the add.
; CHECK: [[REG1:r[0-9]+]] = add([[REG0:r[0-9]+]],#1)
; CHECK: r{{[0-9]+}} = mux(p{{[0-3]}},[[REG1]],[[REG0]])
define i32 @foo(i32 %a, i32 %b) {
%v0 = icmp eq i32 %a, %b
%v1 = zext i1 %v0 to i32
%v2 = add i32 %v1, %a
ret i32 %v2
}