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23 lines
691 B
LLVM
23 lines
691 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Verify __builtin_HEXAGON_V6_vd0 maps to vxor
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; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})
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@g0 = common global <16 x i32> zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0(i32 %a0) #0 {
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b0:
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%v0 = alloca i32, align 4
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store i32 %a0, i32* %v0, align 4
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%v1 = call <16 x i32> @llvm.hexagon.V6.vd0()
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store <16 x i32> %v1, <16 x i32>* @g0, align 64
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ret i32 ptrtoint (<16 x i32>* @g0 to i32)
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vd0() #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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