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ae3819e262
According to PTX ISA .volatile has the same memory synchronization
semantics as .relaxed.sys, so it can be used to implement monotonic
atomic loads and stores. This is important for OpenMP's atomic
construct where
- 'read's and 'write's are lowered to atomic loads and stores, and
- an update of float or double types are lowered into a cmpxchg loop.
(Note that PTX could do better because it has atom.add.f{32,64} but
LLVM's atomicrmw instruction only allows integer types.)
Higher levels of atomicity (like acquire and release) need additional
synchronization properties which were added with PTX ISA 6.0 / sm_70.
So using these instructions still results in an error.
Differential Revision: https://reviews.llvm.org/D50391
llvm-svn: 339316
89 lines
3.0 KiB
LLVM
89 lines
3.0 KiB
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; CHECK-LABEL: plain
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define void @plain(i8* %a, i16* %b, i32* %c, i64* %d) local_unnamed_addr {
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; CHECK: ld.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%a.load = load i8, i8* %a
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%a.add = add i8 %a.load, 1
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; CHECK: st.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store i8 %a.add, i8* %a
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; CHECK: ld.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%b.load = load i16, i16* %b
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%b.add = add i16 %b.load, 1
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; CHECK: st.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store i16 %b.add, i16* %b
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; CHECK: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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%c.load = load i32, i32* %c
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%c.add = add i32 %c.load, 1
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; CHECK: st.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
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store i32 %c.add, i32* %c
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; CHECK: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
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%d.load = load i64, i64* %d
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%d.add = add i64 %d.load, 1
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; CHECK: st.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
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store i64 %d.add, i64* %d
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ret void
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}
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; CHECK-LABEL: volatile
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define void @volatile(i8* %a, i16* %b, i32* %c, i64* %d) local_unnamed_addr {
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; CHECK: ld.volatile.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%a.load = load volatile i8, i8* %a
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%a.add = add i8 %a.load, 1
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; CHECK: st.volatile.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store volatile i8 %a.add, i8* %a
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; CHECK: ld.volatile.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%b.load = load volatile i16, i16* %b
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%b.add = add i16 %b.load, 1
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; CHECK: st.volatile.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store volatile i16 %b.add, i16* %b
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; CHECK: ld.volatile.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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%c.load = load volatile i32, i32* %c
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%c.add = add i32 %c.load, 1
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; CHECK: st.volatile.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
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store volatile i32 %c.add, i32* %c
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; CHECK: ld.volatile.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
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%d.load = load volatile i64, i64* %d
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%d.add = add i64 %d.load, 1
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; CHECK: st.volatile.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
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store volatile i64 %d.add, i64* %d
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ret void
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}
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; CHECK-LABEL: monotonic
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define void @monotonic(i8* %a, i16* %b, i32* %c, i64* %d) local_unnamed_addr {
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; CHECK: ld.volatile.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%a.load = load atomic i8, i8* %a monotonic, align 1
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%a.add = add i8 %a.load, 1
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; CHECK: st.volatile.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store atomic i8 %a.add, i8* %a monotonic, align 1
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; CHECK: ld.volatile.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
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%b.load = load atomic i16, i16* %b monotonic, align 2
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%b.add = add i16 %b.load, 1
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; CHECK: st.volatile.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
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store atomic i16 %b.add, i16* %b monotonic, align 2
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; CHECK: ld.volatile.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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%c.load = load atomic i32, i32* %c monotonic, align 4
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%c.add = add i32 %c.load, 1
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; CHECK: st.volatile.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
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store atomic i32 %c.add, i32* %c monotonic, align 4
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; CHECK: ld.volatile.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
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%d.load = load atomic i64, i64* %d monotonic, align 8
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%d.add = add i64 %d.load, 1
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; CHECK: st.volatile.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
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store atomic i64 %d.add, i64* %d monotonic, align 8
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ret void
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}
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