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https://github.com/RPCS3/llvm-mirror.git
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7084152bd9
Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
40 lines
1.2 KiB
LLVM
40 lines
1.2 KiB
LLVM
; RUN: opt < %s -O3 -S | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define void @no_vectorization(i32 %n, i32 %a, i32 %b) {
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; CHECK-LABEL: no_vectorization(
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; CHECK-NOT: <4 x i32>
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; CHECK-NOT: <4 x i1>
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entry:
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%cmp.5 = icmp sgt i32 %n, 0
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br i1 %cmp.5, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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br label %for.body
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for.cond.cleanup.loopexit: ; preds = %for.body
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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for.body: ; preds = %for.body.preheader, %for.body
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%i.06 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
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%add = add nsw i32 %i.06, %a
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%mul = mul nsw i32 %add, %b
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%cmp1 = icmp sgt i32 %mul, -1
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tail call void @llvm.assume(i1 %cmp1)
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%inc = add nuw nsw i32 %i.06, 1
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%exitcond = icmp eq i32 %inc, %n
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br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
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}
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declare void @llvm.assume(i1) #0
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attributes #0 = { nounwind }
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!nvvm.annotations = !{!0}
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!0 = !{void (i32, i32, i32)* @no_vectorization, !"kernel", i32 1}
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