mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
dcf62df83b
In order to support codegen RV64A, this patch: * Introduces masked atomics intrinsics for atomicrmw operations and cmpxchg that use the i64 type. These are ultimately lowered to masked operations using lr.w/sc.w, but we need to use these alternate intrinsics for RV64 because i32 is not legal * Modifies RISCVExpandPseudoInsts.cpp to handle PseudoAtomicLoadNand64 and PseudoCmpXchg64 * Modifies the AtomicExpandPass hooks in RISCVTargetLowering to sext/trunc as needed for RV64 and to select the i64 intrinsic IDs when necessary * Adds appropriate patterns to RISCVInstrInfoA.td * Updates test/CodeGen/RISCV/atomic-*.ll to show RV64A support This ends up being a fairly mechanical change, as the logic for RV32A is effectively reused. Differential Revision: https://reviews.llvm.org/D53233 llvm-svn: 351422
2724 lines
87 KiB
LLVM
2724 lines
87 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck -check-prefix=RV32I %s
|
|
; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck -check-prefix=RV32IA %s
|
|
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck -check-prefix=RV64I %s
|
|
; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck -check-prefix=RV64IA %s
|
|
|
|
define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_monotonic_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: mv a3, zero
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_monotonic_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB0_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB0_1
|
|
; RV32IA-NEXT: .LBB0_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_monotonic_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: mv a3, zero
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_monotonic_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB0_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB0_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB0_1
|
|
; RV64IA-NEXT: .LBB0_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_acquire_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_acquire_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB1_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB1_1
|
|
; RV32IA-NEXT: .LBB1_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_acquire_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_acquire_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB1_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB1_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB1_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB1_1
|
|
; RV64IA-NEXT: .LBB1_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_acquire_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_acquire_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB2_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB2_1
|
|
; RV32IA-NEXT: .LBB2_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_acquire_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_acquire_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB2_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB2_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB2_1
|
|
; RV64IA-NEXT: .LBB2_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_release_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_release_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB3_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB3_1
|
|
; RV32IA-NEXT: .LBB3_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_release_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_release_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB3_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB3_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB3_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB3_1
|
|
; RV64IA-NEXT: .LBB3_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_release_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_release_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB4_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB4_1
|
|
; RV32IA-NEXT: .LBB4_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_release_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_release_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB4_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB4_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB4_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB4_1
|
|
; RV64IA-NEXT: .LBB4_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_acq_rel_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB5_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB5_1
|
|
; RV32IA-NEXT: .LBB5_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_acq_rel_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_acq_rel_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB5_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB5_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB5_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB5_1
|
|
; RV64IA-NEXT: .LBB5_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_acq_rel_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_acq_rel_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB6_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB6_1
|
|
; RV32IA-NEXT: .LBB6_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_acq_rel_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_acq_rel_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB6_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB6_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB6_1
|
|
; RV64IA-NEXT: .LBB6_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_seq_cst_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB7_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB7_1
|
|
; RV32IA-NEXT: .LBB7_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_seq_cst_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_seq_cst_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB7_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB7_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB7_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB7_1
|
|
; RV64IA-NEXT: .LBB7_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_seq_cst_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_seq_cst_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB8_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB8_1
|
|
; RV32IA-NEXT: .LBB8_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_seq_cst_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_seq_cst_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB8_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB8_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB8_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB8_1
|
|
; RV64IA-NEXT: .LBB8_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) {
|
|
; RV32I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sb a1, 11(sp)
|
|
; RV32I-NEXT: addi a1, sp, 11
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_1
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: slli a3, a0, 3
|
|
; RV32IA-NEXT: andi a3, a3, 24
|
|
; RV32IA-NEXT: addi a4, zero, 255
|
|
; RV32IA-NEXT: sll a4, a4, a3
|
|
; RV32IA-NEXT: andi a2, a2, 255
|
|
; RV32IA-NEXT: sll a2, a2, a3
|
|
; RV32IA-NEXT: andi a1, a1, 255
|
|
; RV32IA-NEXT: sll a1, a1, a3
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: and a5, a3, a4
|
|
; RV32IA-NEXT: bne a5, a1, .LBB9_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a3, a2
|
|
; RV32IA-NEXT: and a5, a5, a4
|
|
; RV32IA-NEXT: xor a5, a3, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB9_1
|
|
; RV32IA-NEXT: .LBB9_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i8_seq_cst_seq_cst:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sb a1, 7(sp)
|
|
; RV64I-NEXT: addi a1, sp, 7
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_1
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i8_seq_cst_seq_cst:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: andi a3, a0, 3
|
|
; RV64IA-NEXT: slli a3, a3, 3
|
|
; RV64IA-NEXT: addi a4, zero, 255
|
|
; RV64IA-NEXT: sllw a4, a4, a3
|
|
; RV64IA-NEXT: andi a2, a2, 255
|
|
; RV64IA-NEXT: sllw a2, a2, a3
|
|
; RV64IA-NEXT: andi a1, a1, 255
|
|
; RV64IA-NEXT: sllw a1, a1, a3
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB9_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: and a5, a3, a4
|
|
; RV64IA-NEXT: bne a5, a1, .LBB9_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB9_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a3, a2
|
|
; RV64IA-NEXT: and a5, a5, a4
|
|
; RV64IA-NEXT: xor a5, a3, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB9_1
|
|
; RV64IA-NEXT: .LBB9_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_monotonic_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: mv a3, zero
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_monotonic_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB10_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB10_1
|
|
; RV32IA-NEXT: .LBB10_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_monotonic_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: mv a3, zero
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_monotonic_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB10_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB10_1
|
|
; RV64IA-NEXT: .LBB10_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_acquire_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_acquire_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB11_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB11_1
|
|
; RV32IA-NEXT: .LBB11_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_acquire_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_acquire_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB11_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB11_1
|
|
; RV64IA-NEXT: .LBB11_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_acquire_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_acquire_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB12_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB12_1
|
|
; RV32IA-NEXT: .LBB12_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_acquire_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_acquire_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB12_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB12_1
|
|
; RV64IA-NEXT: .LBB12_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_release_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_release_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB13_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB13_1
|
|
; RV32IA-NEXT: .LBB13_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_release_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_release_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB13_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB13_1
|
|
; RV64IA-NEXT: .LBB13_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_release_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_release_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB14_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB14_1
|
|
; RV32IA-NEXT: .LBB14_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_release_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_release_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB14_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB14_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB14_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB14_1
|
|
; RV64IA-NEXT: .LBB14_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_acq_rel_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB15_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB15_1
|
|
; RV32IA-NEXT: .LBB15_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_acq_rel_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_acq_rel_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB15_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB15_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB15_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB15_1
|
|
; RV64IA-NEXT: .LBB15_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_acq_rel_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_acq_rel_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB16_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB16_1
|
|
; RV32IA-NEXT: .LBB16_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_acq_rel_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_acq_rel_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB16_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB16_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.rl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB16_1
|
|
; RV64IA-NEXT: .LBB16_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_seq_cst_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB17_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB17_1
|
|
; RV32IA-NEXT: .LBB17_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_seq_cst_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_seq_cst_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB17_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB17_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB17_1
|
|
; RV64IA-NEXT: .LBB17_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_seq_cst_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_seq_cst_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB18_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB18_1
|
|
; RV32IA-NEXT: .LBB18_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_seq_cst_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_seq_cst_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB18_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB18_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB18_1
|
|
; RV64IA-NEXT: .LBB18_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) {
|
|
; RV32I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sh a1, 10(sp)
|
|
; RV32I-NEXT: addi a1, sp, 10
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_2
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: lui a3, 16
|
|
; RV32IA-NEXT: addi a3, a3, -1
|
|
; RV32IA-NEXT: and a1, a1, a3
|
|
; RV32IA-NEXT: and a2, a2, a3
|
|
; RV32IA-NEXT: slli a4, a0, 3
|
|
; RV32IA-NEXT: andi a4, a4, 24
|
|
; RV32IA-NEXT: sll a3, a3, a4
|
|
; RV32IA-NEXT: sll a2, a2, a4
|
|
; RV32IA-NEXT: sll a1, a1, a4
|
|
; RV32IA-NEXT: andi a0, a0, -4
|
|
; RV32IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV32IA-NEXT: and a5, a4, a3
|
|
; RV32IA-NEXT: bne a5, a1, .LBB19_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
|
|
; RV32IA-NEXT: xor a5, a4, a2
|
|
; RV32IA-NEXT: and a5, a5, a3
|
|
; RV32IA-NEXT: xor a5, a4, a5
|
|
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV32IA-NEXT: bnez a5, .LBB19_1
|
|
; RV32IA-NEXT: .LBB19_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i16_seq_cst_seq_cst:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sh a1, 6(sp)
|
|
; RV64I-NEXT: addi a1, sp, 6
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_2
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i16_seq_cst_seq_cst:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: lui a3, 16
|
|
; RV64IA-NEXT: addiw a3, a3, -1
|
|
; RV64IA-NEXT: and a1, a1, a3
|
|
; RV64IA-NEXT: and a2, a2, a3
|
|
; RV64IA-NEXT: andi a4, a0, 3
|
|
; RV64IA-NEXT: slli a4, a4, 3
|
|
; RV64IA-NEXT: sllw a3, a3, a4
|
|
; RV64IA-NEXT: sllw a2, a2, a4
|
|
; RV64IA-NEXT: sllw a1, a1, a4
|
|
; RV64IA-NEXT: andi a0, a0, -4
|
|
; RV64IA-NEXT: .LBB19_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a4, (a0)
|
|
; RV64IA-NEXT: and a5, a4, a3
|
|
; RV64IA-NEXT: bne a5, a1, .LBB19_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB19_1 Depth=1
|
|
; RV64IA-NEXT: xor a5, a4, a2
|
|
; RV64IA-NEXT: and a5, a5, a3
|
|
; RV64IA-NEXT: xor a5, a4, a5
|
|
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a0)
|
|
; RV64IA-NEXT: bnez a5, .LBB19_1
|
|
; RV64IA-NEXT: .LBB19_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_monotonic_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: mv a3, zero
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_monotonic_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB20_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
|
|
; RV32IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB20_1
|
|
; RV32IA-NEXT: .LBB20_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_monotonic_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: mv a3, zero
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_monotonic_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB20_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB20_1 Depth=1
|
|
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB20_1
|
|
; RV64IA-NEXT: .LBB20_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_acquire_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_acquire_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB21_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
|
|
; RV32IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB21_1
|
|
; RV32IA-NEXT: .LBB21_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_acquire_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_acquire_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB21_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
|
|
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB21_1
|
|
; RV64IA-NEXT: .LBB21_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_acquire_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 2
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_acquire_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB22_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
|
|
; RV32IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB22_1
|
|
; RV32IA-NEXT: .LBB22_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_acquire_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_acquire_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB22_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
|
|
; RV64IA-NEXT: sc.w a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB22_1
|
|
; RV64IA-NEXT: .LBB22_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_release_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_release_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB23_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB23_1
|
|
; RV32IA-NEXT: .LBB23_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_release_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_release_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB23_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB23_1
|
|
; RV64IA-NEXT: .LBB23_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_release_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 3
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_release_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB24_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB24_1
|
|
; RV32IA-NEXT: .LBB24_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_release_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_release_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB24_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB24_1
|
|
; RV64IA-NEXT: .LBB24_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_acq_rel_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB25_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB25_1
|
|
; RV32IA-NEXT: .LBB25_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_acq_rel_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_acq_rel_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB25_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB25_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB25_1
|
|
; RV64IA-NEXT: .LBB25_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_acq_rel_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 4
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_acq_rel_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB26_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB26_1
|
|
; RV32IA-NEXT: .LBB26_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_acq_rel_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_acq_rel_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB26_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB26_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB26_1
|
|
; RV64IA-NEXT: .LBB26_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_seq_cst_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB27_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB27_1
|
|
; RV32IA-NEXT: .LBB27_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_seq_cst_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_seq_cst_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB27_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB27_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB27_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB27_1
|
|
; RV64IA-NEXT: .LBB27_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_seq_cst_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_seq_cst_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB28_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB28_1
|
|
; RV32IA-NEXT: .LBB28_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_seq_cst_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_seq_cst_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB28_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB28_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB28_1
|
|
; RV64IA-NEXT: .LBB28_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) {
|
|
; RV32I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a1, 8(sp)
|
|
; RV32I-NEXT: addi a1, sp, 8
|
|
; RV32I-NEXT: addi a3, zero, 5
|
|
; RV32I-NEXT: mv a4, a3
|
|
; RV32I-NEXT: call __atomic_compare_exchange_4
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
|
|
; RV32IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV32IA-NEXT: bne a3, a1, .LBB29_3
|
|
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
|
|
; RV32IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV32IA-NEXT: bnez a4, .LBB29_1
|
|
; RV32IA-NEXT: .LBB29_3:
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i32_seq_cst_seq_cst:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sw a1, 4(sp)
|
|
; RV64I-NEXT: addi a1, sp, 4
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_4
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.w.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB29_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB29_1 Depth=1
|
|
; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB29_1
|
|
; RV64IA-NEXT: .LBB29_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_monotonic_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a4
|
|
; RV32I-NEXT: mv a4, zero
|
|
; RV32I-NEXT: mv a5, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_monotonic_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a4
|
|
; RV32IA-NEXT: mv a4, zero
|
|
; RV32IA-NEXT: mv a5, zero
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_monotonic_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: mv a3, zero
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_monotonic_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB30_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB30_1 Depth=1
|
|
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB30_1
|
|
; RV64IA-NEXT: .LBB30_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_acquire_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a5, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 2
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a5
|
|
; RV32I-NEXT: mv a5, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_acquire_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a5, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 2
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a5
|
|
; RV32IA-NEXT: mv a5, zero
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_acquire_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_acquire_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB31_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB31_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB31_1 Depth=1
|
|
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB31_1
|
|
; RV64IA-NEXT: .LBB31_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_acquire_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a5, zero, 2
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a4
|
|
; RV32I-NEXT: mv a4, a5
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_acquire_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a5, zero, 2
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a4
|
|
; RV32IA-NEXT: mv a4, a5
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_acquire_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 2
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_acquire_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB32_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB32_1 Depth=1
|
|
; RV64IA-NEXT: sc.d a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB32_1
|
|
; RV64IA-NEXT: .LBB32_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_release_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a5, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 3
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a5
|
|
; RV32I-NEXT: mv a5, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_release_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a5, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 3
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a5
|
|
; RV32IA-NEXT: mv a5, zero
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_release_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_release_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB33_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB33_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB33_1
|
|
; RV64IA-NEXT: .LBB33_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_release_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a6, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 3
|
|
; RV32I-NEXT: addi a5, zero, 2
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a6
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_release_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a6, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 3
|
|
; RV32IA-NEXT: addi a5, zero, 2
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a6
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_release_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 3
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_release_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB34_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB34_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB34_1
|
|
; RV64IA-NEXT: .LBB34_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_acq_rel_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a5, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 4
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a5
|
|
; RV32I-NEXT: mv a5, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a5, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 4
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a5
|
|
; RV32IA-NEXT: mv a5, zero
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_acq_rel_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_acq_rel_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB35_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB35_1
|
|
; RV64IA-NEXT: .LBB35_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_acq_rel_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a6, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 4
|
|
; RV32I-NEXT: addi a5, zero, 2
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a6
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_acq_rel_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a6, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 4
|
|
; RV32IA-NEXT: addi a5, zero, 2
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a6
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_acq_rel_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 4
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_acq_rel_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aq a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB36_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.rl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB36_1
|
|
; RV64IA-NEXT: .LBB36_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_seq_cst_monotonic:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a5, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 5
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a5
|
|
; RV32I-NEXT: mv a5, zero
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a5, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 5
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a5
|
|
; RV32IA-NEXT: mv a5, zero
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_seq_cst_monotonic:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, zero
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_seq_cst_monotonic:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB37_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB37_1
|
|
; RV64IA-NEXT: .LBB37_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_seq_cst_acquire:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: mv a6, a4
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a4, zero, 5
|
|
; RV32I-NEXT: addi a5, zero, 2
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a6
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_seq_cst_acquire:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: mv a6, a4
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a4, zero, 5
|
|
; RV32IA-NEXT: addi a5, zero, 2
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a6
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_seq_cst_acquire:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: addi a4, zero, 2
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_seq_cst_acquire:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB38_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB38_1
|
|
; RV64IA-NEXT: .LBB38_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
|
|
ret void
|
|
}
|
|
|
|
define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) {
|
|
; RV32I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi sp, sp, -16
|
|
; RV32I-NEXT: sw ra, 12(sp)
|
|
; RV32I-NEXT: sw a2, 4(sp)
|
|
; RV32I-NEXT: sw a1, 0(sp)
|
|
; RV32I-NEXT: mv a1, sp
|
|
; RV32I-NEXT: addi a5, zero, 5
|
|
; RV32I-NEXT: mv a2, a3
|
|
; RV32I-NEXT: mv a3, a4
|
|
; RV32I-NEXT: mv a4, a5
|
|
; RV32I-NEXT: call __atomic_compare_exchange_8
|
|
; RV32I-NEXT: lw ra, 12(sp)
|
|
; RV32I-NEXT: addi sp, sp, 16
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
|
|
; RV32IA: # %bb.0:
|
|
; RV32IA-NEXT: addi sp, sp, -16
|
|
; RV32IA-NEXT: sw ra, 12(sp)
|
|
; RV32IA-NEXT: sw a2, 4(sp)
|
|
; RV32IA-NEXT: sw a1, 0(sp)
|
|
; RV32IA-NEXT: mv a1, sp
|
|
; RV32IA-NEXT: addi a5, zero, 5
|
|
; RV32IA-NEXT: mv a2, a3
|
|
; RV32IA-NEXT: mv a3, a4
|
|
; RV32IA-NEXT: mv a4, a5
|
|
; RV32IA-NEXT: call __atomic_compare_exchange_8
|
|
; RV32IA-NEXT: lw ra, 12(sp)
|
|
; RV32IA-NEXT: addi sp, sp, 16
|
|
; RV32IA-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: cmpxchg_i64_seq_cst_seq_cst:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: addi sp, sp, -16
|
|
; RV64I-NEXT: sd ra, 8(sp)
|
|
; RV64I-NEXT: sd a1, 0(sp)
|
|
; RV64I-NEXT: mv a1, sp
|
|
; RV64I-NEXT: addi a3, zero, 5
|
|
; RV64I-NEXT: mv a4, a3
|
|
; RV64I-NEXT: call __atomic_compare_exchange_8
|
|
; RV64I-NEXT: ld ra, 8(sp)
|
|
; RV64I-NEXT: addi sp, sp, 16
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV64IA-LABEL: cmpxchg_i64_seq_cst_seq_cst:
|
|
; RV64IA: # %bb.0:
|
|
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
|
|
; RV64IA-NEXT: lr.d.aqrl a3, (a0)
|
|
; RV64IA-NEXT: bne a3, a1, .LBB39_3
|
|
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
|
|
; RV64IA-NEXT: sc.d.aqrl a4, a2, (a0)
|
|
; RV64IA-NEXT: bnez a4, .LBB39_1
|
|
; RV64IA-NEXT: .LBB39_3:
|
|
; RV64IA-NEXT: ret
|
|
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
|
|
ret void
|
|
}
|