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bc658bf60a
This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; Test loads of f128 floating-point constants on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CONST
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; Test loading zero.
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define void @f1(fp128 *%x) {
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; CHECK-LABEL: f1:
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; CHECK: vzero [[REG:%v[0-9]+]]
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; CHECK: vst [[REG]], 0(%r2)
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; CHECK: br %r14
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store fp128 0xL00000000000000000000000000000000, fp128 *%x
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ret void
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}
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; Test loading of negative floating-point zero.
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define void @f2(fp128 *%x) {
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; CHECK-LABEL: f2:
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; CHECK: vzero [[REG:%v[0-9]+]]
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; CHECK: wflnxb [[REG]], [[REG]]
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; CHECK: vst [[REG]], 0(%r2)
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; CHECK: br %r14
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store fp128 0xL00000000000000008000000000000000, fp128 *%x
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ret void
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}
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; Test loading of a 128-bit floating-point constant. This value would
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; actually fit within the 32-bit format, but we don't have extending
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; loads into vector registers.
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define void @f3(fp128 *%x) {
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; CHECK-LABEL: f3:
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; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
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; CHECK: vl [[REG:%v[0-9]+]], 0([[REGISTER]])
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; CHECK: vst [[REG]], 0(%r2)
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; CHECK: br %r14
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; CONST: .quad 4611404543484231680
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; CONST: .quad 0
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store fp128 0xL00000000000000003fff000002000000, fp128 *%x
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ret void
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}
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