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I have added a new file: llvm/test/CodeGen/AArch64/README that describes what to do in the event one of the SVE codegen tests fails the warnings check. In addition, I've added comments to all the relevant SVE tests pointing users at the README file. Differential Revision: https://reviews.llvm.org/D83467
107 lines
3.5 KiB
LLVM
107 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; ST1B
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define void @st1b_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
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; CHECK-LABEL: st1b_lower_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0, #-8, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -8
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store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
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ret void
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}
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define void @st1b_inbound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
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; CHECK-LABEL: st1b_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 1
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store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
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ret void
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}
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define void @st1b_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
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; CHECK-LABEL: st1b_upper_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 7
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store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
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ret void
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}
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define void @st1b_out_of_upper_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
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; CHECK-LABEL: st1b_out_of_upper_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #8
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x8]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 8
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store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
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ret void
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}
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define void @st1b_out_of_lower_bound(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %a) {
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; CHECK-LABEL: st1b_out_of_lower_bound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #-9
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: st1b { z0.b }, p0, [x8]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %a, i64 -9
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store <vscale x 16 x i8> %data, <vscale x 16 x i8>* %base
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ret void
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}
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; ST1H
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define void @st1h_inbound(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %a) {
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; CHECK-LABEL: st1h_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0, #-6, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %a, i64 -6
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store <vscale x 8 x i16> %data, <vscale x 8 x i16>* %base
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ret void
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}
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; ST1W
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define void @st1w_inbound(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %a) {
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; CHECK-LABEL: st1w_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %a, i64 2
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store <vscale x 4 x i32> %data, <vscale x 4 x i32>* %base
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ret void
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}
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; ST1D
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define void @st1d_inbound(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %a) {
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; CHECK-LABEL: st1d_inbound:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: st1d { z0.d }, p0, [x0, #5, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %a, i64 5
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store <vscale x 2 x i64> %data, <vscale x 2 x i64>* %base
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ret void
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}
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