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b9ecf8a3ee
This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D12985 llvm-svn: 248887
26 lines
1.2 KiB
LLVM
26 lines
1.2 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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; The alignment arguments for NEON load/store intrinsics can be increased
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; by instcombine. Check for this.
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; CHECK: vld4.v2i32.p0i8({{.*}}, i32 32)
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; CHECK: vst4.p0i8.v2i32({{.*}}, i32 16)
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@x = common global [8 x i32] zeroinitializer, align 32
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@y = common global [8 x i32] zeroinitializer, align 16
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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define void @test() nounwind ssp {
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%tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8* bitcast ([8 x i32]* @x to i8*), i32 1)
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%tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 1
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%tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2
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%tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 3
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call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* bitcast ([8 x i32]* @y to i8*), <2 x i32> %tmp2, <2 x i32> %tmp3, <2 x i32> %tmp4, <2 x i32> %tmp5, i32 1)
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ret void
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}
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8*, i32) nounwind readonly
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declare void @llvm.arm.neon.vst4.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
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