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8576aee95c
The way we elide max expressions when computing trip counts is incorrect
-- it breaks cases like this:
```
static int wrapping_add(int a, int b) {
return (int)((unsigned)a + (unsigned)b);
}
void test() {
volatile int end_buf = 2147483548; // INT_MIN - 100
int end = end_buf;
unsigned counter = 0;
for (int start = wrapping_add(end, 200); start < end; start++)
counter++;
print(counter);
}
```
Note: the `NoWrap` variable that was being tested has little to do with
the values flowing into the max expression; it is a property of the
induction variable.
test/Transforms/LoopUnroll/nsw-tripcount.ll was added to solely test
functionality I'm reverting in this change, so I've deleted the test
fully.
llvm-svn: 273079
263 lines
8.5 KiB
LLVM
263 lines
8.5 KiB
LLVM
; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
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; The addrecs in this loop are analyzable only by using nsw information.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
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; CHECK: Classifying expressions for: @test1
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define void @test1(double* %p) nounwind {
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entry:
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%tmp = load double, double* %p, align 8 ; <double> [#uses=1]
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%tmp1 = fcmp ogt double %tmp, 2.000000e+00 ; <i1> [#uses=1]
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br i1 %tmp1, label %bb.nph, label %return
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bb.nph: ; preds = %entry
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br label %bb
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bb: ; preds = %bb1, %bb.nph
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%i.01 = phi i32 [ %tmp8, %bb1 ], [ 0, %bb.nph ] ; <i32> [#uses=3]
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; CHECK: %i.01
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; CHECK-NEXT: --> {0,+,1}<nuw><nsw><%bb>
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%tmp2 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
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%tmp3 = getelementptr double, double* %p, i64 %tmp2 ; <double*> [#uses=1]
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%tmp4 = load double, double* %tmp3, align 8 ; <double> [#uses=1]
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%tmp5 = fmul double %tmp4, 9.200000e+00 ; <double> [#uses=1]
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%tmp6 = sext i32 %i.01 to i64 ; <i64> [#uses=1]
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%tmp7 = getelementptr double, double* %p, i64 %tmp6 ; <double*> [#uses=1]
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; CHECK: %tmp7
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; CHECK-NEXT: --> {%p,+,8}<%bb>
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store double %tmp5, double* %tmp7, align 8
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%tmp8 = add nsw i32 %i.01, 1 ; <i32> [#uses=2]
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; CHECK: %tmp8
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; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%bb>
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%p.gep = getelementptr double, double* %p, i32 %tmp8
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%p.val = load double, double* %p.gep
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br label %bb1
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bb1: ; preds = %bb
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%phitmp = sext i32 %tmp8 to i64 ; <i64> [#uses=1]
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; CHECK: %phitmp
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; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%bb>
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%tmp9 = getelementptr inbounds double, double* %p, i64 %phitmp ; <double*> [#uses=1]
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; CHECK: %tmp9
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; CHECK-NEXT: --> {(8 + %p)<nsw>,+,8}<nsw><%bb>
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%tmp10 = load double, double* %tmp9, align 8 ; <double> [#uses=1]
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%tmp11 = fcmp ogt double %tmp10, 2.000000e+00 ; <i1> [#uses=1]
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br i1 %tmp11, label %bb, label %bb1.return_crit_edge
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bb1.return_crit_edge: ; preds = %bb1
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br label %return
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return: ; preds = %bb1.return_crit_edge, %entry
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ret void
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}
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; CHECK: Classifying expressions for: @test2
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define void @test2(i32* %begin, i32* %end) ssp {
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entry:
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%cmp1.i.i = icmp eq i32* %begin, %end
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br i1 %cmp1.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.lr.ph.i.i
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for.body.lr.ph.i.i: ; preds = %entry
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br label %for.body.i.i
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for.body.i.i: ; preds = %for.body.i.i, %for.body.lr.ph.i.i
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%__first.addr.02.i.i = phi i32* [ %begin, %for.body.lr.ph.i.i ], [ %ptrincdec.i.i, %for.body.i.i ]
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; CHECK: %__first.addr.02.i.i
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; CHECK-NEXT: --> {%begin,+,4}<nuw><%for.body.i.i>
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store i32 0, i32* %__first.addr.02.i.i, align 4
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%ptrincdec.i.i = getelementptr inbounds i32, i32* %__first.addr.02.i.i, i64 1
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; CHECK: %ptrincdec.i.i
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; CHECK-NEXT: --> {(4 + %begin)<nsw>,+,4}<nuw><%for.body.i.i>
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%cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end
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br i1 %cmp.i.i, label %for.cond.for.end_crit_edge.i.i, label %for.body.i.i
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for.cond.for.end_crit_edge.i.i: ; preds = %for.body.i.i
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br label %_ZSt4fillIPiiEvT_S1_RKT0_.exit
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_ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %entry, %for.cond.for.end_crit_edge.i.i
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ret void
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}
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; Various checks for inbounds geps.
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define void @test3(i32* %begin, i32* %end) nounwind ssp {
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entry:
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%cmp7.i.i = icmp eq i32* %begin, %end
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br i1 %cmp7.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i
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for.body.i.i: ; preds = %entry, %for.body.i.i
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%indvar.i.i = phi i64 [ %tmp, %for.body.i.i ], [ 0, %entry ]
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; CHECK: %indvar.i.i
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; CHECK: {0,+,1}<nuw><nsw><%for.body.i.i>
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%tmp = add nsw i64 %indvar.i.i, 1
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; CHECK: %tmp =
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; CHECK: {1,+,1}<nuw><nsw><%for.body.i.i>
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%ptrincdec.i.i = getelementptr inbounds i32, i32* %begin, i64 %tmp
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; CHECK: %ptrincdec.i.i =
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; CHECK: {(4 + %begin)<nsw>,+,4}<nsw><%for.body.i.i>
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%__first.addr.08.i.i = getelementptr inbounds i32, i32* %begin, i64 %indvar.i.i
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; CHECK: %__first.addr.08.i.i
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; CHECK: {%begin,+,4}<nsw><%for.body.i.i>
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store i32 0, i32* %__first.addr.08.i.i, align 4
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%cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end
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br i1 %cmp.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i
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; CHECK: Loop %for.body.i.i: backedge-taken count is ((-4 + (-1 * %begin) + %end) /u 4)
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; CHECK: Loop %for.body.i.i: max backedge-taken count is ((-4 + (-1 * %begin) + %end) /u 4)
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_ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %for.body.i.i, %entry
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ret void
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}
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; A single AddExpr exists for (%a + %b), which is not always <nsw>.
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; CHECK: @addnsw
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; CHECK-NOT: --> (%a + %b)<nsw>
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define i32 @addnsw(i32 %a, i32 %b) nounwind ssp {
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entry:
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%tmp = add i32 %a, %b
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%cmp = icmp sgt i32 %tmp, 0
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br i1 %cmp, label %greater, label %exit
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greater:
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%tmp2 = add nsw i32 %a, %b
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br label %exit
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exit:
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%result = phi i32 [ %a, %entry ], [ %tmp2, %greater ]
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ret i32 %result
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}
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; CHECK-LABEL: PR12375
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; CHECK: --> {(4 + %arg)<nsw>,+,4}<nuw><%bb1>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (4 + (4 * ((-1 + (-1 * %arg) + ((4 + %arg)<nsw> umax (8 + %arg)<nsw>)) /u 4)) + %arg)
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define i32 @PR12375(i32* readnone %arg) {
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bb:
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%tmp = getelementptr inbounds i32, i32* %arg, i64 2
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br label %bb1
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bb1: ; preds = %bb1, %bb
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%tmp2 = phi i32* [ %arg, %bb ], [ %tmp5, %bb1 ]
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%tmp3 = phi i32 [ 0, %bb ], [ %tmp4, %bb1 ]
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%tmp4 = add nsw i32 %tmp3, 1
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%tmp5 = getelementptr inbounds i32, i32* %tmp2, i64 1
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%tmp6 = icmp ult i32* %tmp5, %tmp
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br i1 %tmp6, label %bb1, label %bb7
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bb7: ; preds = %bb1
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ret i32 %tmp4
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}
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; CHECK-LABEL: PR12376
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; CHECK: --> {(4 + %arg)<nsw>,+,4}<nuw><%bb2>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (4 + (4 * ((-1 + (-1 * %arg) + ((4 + %arg)<nsw> umax %arg1)) /u 4)) + %arg)
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define void @PR12376(i32* nocapture %arg, i32* nocapture %arg1) {
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bb:
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br label %bb2
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bb2: ; preds = %bb2, %bb
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%tmp = phi i32* [ %arg, %bb ], [ %tmp4, %bb2 ]
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%tmp4 = getelementptr inbounds i32, i32* %tmp, i64 1
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%tmp3 = icmp ult i32* %tmp4, %arg1
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br i1 %tmp3, label %bb2, label %bb5
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bb5: ; preds = %bb2
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ret void
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}
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declare void @f(i32)
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; CHECK-LABEL: nswnowrap
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; CHECK: --> {(1 + %v)<nsw>,+,1}<nsw><%for.body>{{ U: [^ ]+ S: [^ ]+}}{{ *}}Exits: (1 + ((1 + %v)<nsw> smax %v))
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define void @nswnowrap(i32 %v, i32* %buf) {
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entry:
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%add = add nsw i32 %v, 1
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br label %for.body
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for.body:
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%i.04 = phi i32 [ %v, %entry ], [ %inc, %for.body ]
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%inc = add nsw i32 %i.04, 1
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%buf.gep = getelementptr inbounds i32, i32* %buf, i32 %inc
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%buf.val = load i32, i32* %buf.gep
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%cmp = icmp slt i32 %i.04, %add
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tail call void @f(i32 %i.04)
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret void
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}
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; This test checks if no-wrap flags are propagated when folding {S,+,X}+T ==> {S+T,+,X}
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; CHECK-LABEL: test4
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; CHECK: %idxprom
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; CHECK-NEXT: --> {(-2 + (sext i32 %arg to i64))<nsw>,+,1}<nsw><%for.body>
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define void @test4(i32 %arg) {
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entry:
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%array = alloca [10 x i32], align 4
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br label %for.body
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for.body:
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%index = phi i32 [ %inc5, %for.body ], [ %arg, %entry ]
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%sub = add nsw i32 %index, -2
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%idxprom = sext i32 %sub to i64
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%arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* %array, i64 0, i64 %idxprom
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%data = load i32, i32* %arrayidx, align 4
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%inc5 = add nsw i32 %index, 1
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%cmp2 = icmp slt i32 %inc5, 10
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br i1 %cmp2, label %for.body, label %for.end
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for.end:
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ret void
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}
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define void @bad_postinc_nsw_a(i32 %n) {
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; CHECK-LABEL: Classifying expressions for: @bad_postinc_nsw_a
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
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%iv.inc = add nsw i32 %iv, 7
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; CHECK: %iv.inc = add nsw i32 %iv, 7
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; CHECK-NEXT: --> {7,+,7}<nuw><%loop>
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%becond = icmp ult i32 %iv, %n
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br i1 %becond, label %loop, label %leave
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leave:
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ret void
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}
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define void @bad_postinc_nsw_b(i32 %n) {
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; CHECK-LABEL: Classifying expressions for: @bad_postinc_nsw_b
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
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%iv.inc = add nsw i32 %iv, 7
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%iv.inc.and = and i32 %iv.inc, 0
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; CHECK: %iv.inc = add nsw i32 %iv, 7
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; CHECK-NEXT: --> {7,+,7}<nuw><%loop>
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%becond = icmp ult i32 %iv.inc.and, %n
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br i1 %becond, label %loop, label %leave
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leave:
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ret void
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}
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declare void @may_exit() nounwind
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define void @pr28012(i32 %n) {
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; CHECK-LABEL: Classifying expressions for: @pr28012
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.inc, %loop ]
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%iv.inc = add nsw i32 %iv, 7
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; CHECK: %iv.inc = add nsw i32 %iv, 7
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; CHECK-NEXT: --> {7,+,7}<nuw><%loop>
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%becond = icmp ult i32 %iv.inc, %n
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call void @may_exit()
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br i1 %becond, label %loop, label %leave
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leave:
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ret void
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}
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