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a4a46c15fe
Summary:
Two exceptions to this:
test/CodeGen/Mips/octeon.ll
test/CodeGen/Mips/octeon_popcnt.ll
these test extensions to MIPS64
One test is altered for MIPS-IV:
test/CodeGen/Mips/mips64countleading.ll
Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests
that dclo/dclz are not emitted.
Four tests fail and are not in this patch:
test/CodeGen/Mips/abicalls.ll
test/CodeGen/Mips/fcopysign-f32-f64.ll
test/CodeGen/Mips/fcopysign.ll
test/CodeGen/Mips/stack-alignment.ll
Depends on D3343
Reviewers: matheusalmeida, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3344
llvm-svn: 206185
53 lines
1.0 KiB
LLVM
53 lines
1.0 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
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; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=64
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=64
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define void @f0() nounwind {
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entry:
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; 32: addiu $4, $zero, 1
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; 32: addiu $4, $zero, 1
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tail call void @foo1(i32 1) nounwind
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tail call void @foo1(i32 1) nounwind
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ret void
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}
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declare void @foo1(i32)
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define void @f3() nounwind {
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entry:
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; 64: daddiu $4, $zero, 1
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; 64: daddiu $4, $zero, 1
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tail call void @foo2(i64 1) nounwind
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tail call void @foo2(i64 1) nounwind
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ret void
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}
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declare void @foo2(i64)
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define void @f5() nounwind {
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entry:
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; 32: lui $4, 1
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; 32: lui $4, 1
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tail call void @f6(i32 65536) nounwind
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tail call void @f6(i32 65536) nounwind
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ret void
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}
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declare void @f6(i32)
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define void @f7() nounwind {
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entry:
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; 64: lui $4, 1
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; 64: lui $4, 1
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tail call void @f8(i64 65536) nounwind
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tail call void @f8(i64 65536) nounwind
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ret void
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}
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declare void @f8(i64)
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