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5b7d6ac920
The index reg on instructions with complex address modes is a GPR64_NOSP. Constrain it to appease the machine verifier. llvm-svn: 236557
26 lines
839 B
LLVM
26 lines
839 B
LLVM
; RUN: llc %s -o - -verify-machineinstrs | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-unknown"
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@TheArray = external global [100000 x double], align 16
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; This test ensures, via the machine verifier, that the register class for the
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; index of the double store is correctly constrained to not include SP.
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; CHECK: movsd
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define i32 @main(i32* %i, double %tmpv) {
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bb:
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br label %bb7
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bb7: ; preds = %bb7, %bb
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%storemerge = phi i32 [ 0, %bb ], [ %tmp19, %bb7 ]
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%tmp15 = zext i32 %storemerge to i64
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%tmp16 = getelementptr inbounds [100000 x double], [100000 x double]* @TheArray, i64 0, i64 %tmp15
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store double %tmpv, double* %tmp16, align 8
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%tmp18 = load i32, i32* %i, align 4
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%tmp19 = add i32 %tmp18, 1
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br label %bb7
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}
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