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3bdc5396f2
On the ppc64le platform, if ir has the following form, define i64 @addze1(i64 %x, i64 %z) local_unnamed_addr #0 { entry: %cmp = icmp ne i64 %z, CONSTANT (-32767 <= CONSTANT <= 32768) %conv1 = zext i1 %cmp to i64 %add = add nsw i64 %conv1, %x ret i64 %add } we can optimize it to the form below. when C == 0 --> addze X, (addic Z, -1)) / add X, (zext(setne Z, C))-- \ when -32768 <= -C <= 32767 && C != 0 --> addze X, (addic (addi Z, -C), -1) Patch By: HLJ2009 (Li Jia He) Differential Revision: https://reviews.llvm.org/D51403 Reviewed By: Nemanjai llvm-svn: 341634
173 lines
5.0 KiB
LLVM
173 lines
5.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr9 < %s | FileCheck %s
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define i64 @addze1(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addic [[REG1:r[0-9]+]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 0
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze2(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subfic [[REG1:r[0-9]+]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 0
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze3(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
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; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze4(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], -32768
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; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze5(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
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; CHECK-NEXT: addic [[REG1]], [[REG1]], -1
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, -32767
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @addze6(i64 %X, i64 %Z) {
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; CHECK-LABEL: addze6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi [[REG1:r[0-9]+]], [[REG1]], 32767
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; CHECK-NEXT: subfic [[REG1]], [[REG1]], 0
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; CHECK-NEXT: addze [[REG2:r[0-9]+]], [[REG2]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, -32767
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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; element is out of range
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define i64 @test1(i64 %X, i64 %Z) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, -32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test2(i64 %X, i64 %Z) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, -32768
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test3(i64 %X, i64 %Z) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
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; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Z, 32769
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test4(i64 %X, i64 %Z) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
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; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Z, 32769
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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; comparison of two registers
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define i64 @test5(i64 %X, i64 %Y, i64 %Z) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
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; CHECK-NEXT: addic [[REG1]], [[REG2]], -1
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; CHECK-NEXT: subfe [[REG2]], [[REG1]], [[REG2]]
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp ne i64 %Y, %Z
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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define i64 @test6(i64 %X, i64 %Y, i64 %Z) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
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; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
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; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
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; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: blr
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%cmp = icmp eq i64 %Y, %Z
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%conv1 = zext i1 %cmp to i64
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%add = add nsw i64 %conv1, %X
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ret i64 %add
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}
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