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97fd4517d5
This patch implements a target independent DAG combine to produce multiply-high instructions from shifts. This DAG combine will combine shifts for any type as long as the MULH on the narrow type is legal. For now, it is enabled on PowerPC as PowerPC is the only target that has an implementation of the isMulhCheaperThanMulShift TLI hook introduced in D78271. Moreover, this DAG combine focuses on catching the pattern: (shift (mul (ext <narrow_type>:$a to <wide_type>), (ext <narrow_type>:$b to <wide_type>)), <narrow_width>) to produce mulhs when we have a sign-extend, and mulhu when we have a zero-extend. The patch performs the following checks: - Operation is a right shift arithmetic (sra) or logical (srl) - Input to the shift is a multiply - Both operands to the shift are sext/zext nodes - The extends into the multiply are both the same - The narrow type is half the width of the wide type - The shift amount is the width of the narrow type - The respective mulh operation is legal Differential Revision: https://reviews.llvm.org/D78272
126 lines
3.5 KiB
LLVM
126 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; This test case tests multiply high for i32 and i64. When the values are
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; sign-extended, mulh[d|w] is emitted. When values are zero-extended,
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; mulh[d|w]u is emitted instead.
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; The primary goal is transforming the pattern:
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; (shift (mul (ext $a, <wide_type>), (ext $b, <wide_type>)), <narrow_type>)
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; into (mulhs $a, $b) for sign extend, and (mulhu $a, $b) for zero extend,
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; provided that the mulh operation is legal for <narrow_type>.
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; The shift operation can be either the srl or sra operations.
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; When no attribute is present on i32, the shift operation is srl.
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define i32 @test_mulhw(i32 %a, i32 %b) {
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; CHECK-LABEL: test_mulhw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhw r3, r3, r4
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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%1 = sext i32 %a to i64
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%2 = sext i32 %b to i64
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%mul = mul i64 %1, %2
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%shr = lshr i64 %mul, 32
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%tr = trunc i64 %shr to i32
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ret i32 %tr
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}
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define i32 @test_mulhu(i32 %a, i32 %b) {
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; CHECK-LABEL: test_mulhu:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhwu r3, r3, r4
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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%1 = zext i32 %a to i64
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%2 = zext i32 %b to i64
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%mul = mul i64 %1, %2
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%shr = lshr i64 %mul, 32
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%tr = trunc i64 %shr to i32
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ret i32 %tr
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}
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define i64 @test_mulhd(i64 %a, i64 %b) {
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; CHECK-LABEL: test_mulhd:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhd r3, r3, r4
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; CHECK-NEXT: blr
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%1 = sext i64 %a to i128
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%2 = sext i64 %b to i128
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%mul = mul i128 %1, %2
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%shr = lshr i128 %mul, 64
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%tr = trunc i128 %shr to i64
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ret i64 %tr
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}
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define i64 @test_mulhdu(i64 %a, i64 %b) {
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; CHECK-LABEL: test_mulhdu:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhdu r3, r3, r4
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; CHECK-NEXT: blr
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%1 = zext i64 %a to i128
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%2 = zext i64 %b to i128
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%mul = mul i128 %1, %2
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%shr = lshr i128 %mul, 64
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%tr = trunc i128 %shr to i64
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ret i64 %tr
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}
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; When the signext attribute is present on i32, the shift operation is sra.
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; We are actually transforming (sra (mul sext_in_reg, sext_in_reg)) into mulh.
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define signext i32 @test_mulhw_signext(i32 %a, i32 %b) {
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; CHECK-LABEL: test_mulhw_signext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhw r3, r3, r4
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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%1 = sext i32 %a to i64
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%2 = sext i32 %b to i64
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%mul = mul i64 %1, %2
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%shr = lshr i64 %mul, 32
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%tr = trunc i64 %shr to i32
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ret i32 %tr
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}
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define zeroext i32 @test_mulhu_zeroext(i32 %a, i32 %b) {
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; CHECK-LABEL: test_mulhu_zeroext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhwu r3, r3, r4
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: blr
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%1 = zext i32 %a to i64
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%2 = zext i32 %b to i64
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%mul = mul i64 %1, %2
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%shr = lshr i64 %mul, 32
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%tr = trunc i64 %shr to i32
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ret i32 %tr
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}
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define signext i64 @test_mulhd_signext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_mulhd_signext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhd r3, r3, r4
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; CHECK-NEXT: blr
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%1 = sext i64 %a to i128
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%2 = sext i64 %b to i128
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%mul = mul i128 %1, %2
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%shr = lshr i128 %mul, 64
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%tr = trunc i128 %shr to i64
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ret i64 %tr
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}
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define zeroext i64 @test_mulhdu_zeroext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_mulhdu_zeroext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mulhdu r3, r3, r4
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; CHECK-NEXT: blr
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%1 = zext i64 %a to i128
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%2 = zext i64 %b to i128
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%mul = mul i128 %1, %2
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%shr = lshr i128 %mul, 64
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%tr = trunc i128 %shr to i64
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ret i64 %tr
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}
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