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279 lines
9.1 KiB
C++
279 lines
9.1 KiB
C++
//===- GCNRegPressure.h -----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the GCNRegPressure class, which tracks registry pressure
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/// by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs. It
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/// also implements a compare function, which compares different register
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/// pressures, and declares one with max occupance as winner.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
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#define LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
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#include "AMDGPUSubtarget.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/MC/LaneBitmask.h"
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#include "llvm/Support/Debug.h"
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#include <algorithm>
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#include <limits>
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namespace llvm {
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class MachineRegisterInfo;
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class raw_ostream;
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struct GCNRegPressure {
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enum RegKind {
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SGPR32,
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SGPR_TUPLE,
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VGPR32,
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VGPR_TUPLE,
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AGPR32,
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AGPR_TUPLE,
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TOTAL_KINDS
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};
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GCNRegPressure() {
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clear();
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}
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bool empty() const { return getSGPRNum() == 0 && getVGPRNum() == 0; }
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void clear() { std::fill(&Value[0], &Value[TOTAL_KINDS], 0); }
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unsigned getSGPRNum() const { return Value[SGPR32]; }
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unsigned getVGPRNum() const { return std::max(Value[VGPR32], Value[AGPR32]); }
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unsigned getVGPRTuplesWeight() const { return std::max(Value[VGPR_TUPLE],
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Value[AGPR_TUPLE]); }
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unsigned getSGPRTuplesWeight() const { return Value[SGPR_TUPLE]; }
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unsigned getOccupancy(const GCNSubtarget &ST) const {
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return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
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ST.getOccupancyWithNumVGPRs(getVGPRNum()));
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}
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void inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,
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const MachineRegisterInfo &MRI);
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bool higherOccupancy(const GCNSubtarget &ST, const GCNRegPressure& O) const {
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return getOccupancy(ST) > O.getOccupancy(ST);
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}
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bool less(const GCNSubtarget &ST, const GCNRegPressure& O,
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unsigned MaxOccupancy = std::numeric_limits<unsigned>::max()) const;
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bool operator==(const GCNRegPressure &O) const {
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return std::equal(&Value[0], &Value[TOTAL_KINDS], O.Value);
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}
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bool operator!=(const GCNRegPressure &O) const {
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return !(*this == O);
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}
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void print(raw_ostream &OS, const GCNSubtarget *ST = nullptr) const;
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void dump() const { print(dbgs()); }
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private:
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unsigned Value[TOTAL_KINDS];
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static unsigned getRegKind(Register Reg, const MachineRegisterInfo &MRI);
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friend GCNRegPressure max(const GCNRegPressure &P1,
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const GCNRegPressure &P2);
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};
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inline GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2) {
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GCNRegPressure Res;
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for (unsigned I = 0; I < GCNRegPressure::TOTAL_KINDS; ++I)
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Res.Value[I] = std::max(P1.Value[I], P2.Value[I]);
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return Res;
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}
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class GCNRPTracker {
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public:
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using LiveRegSet = DenseMap<unsigned, LaneBitmask>;
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protected:
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const LiveIntervals &LIS;
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LiveRegSet LiveRegs;
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GCNRegPressure CurPressure, MaxPressure;
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const MachineInstr *LastTrackedMI = nullptr;
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mutable const MachineRegisterInfo *MRI = nullptr;
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GCNRPTracker(const LiveIntervals &LIS_) : LIS(LIS_) {}
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void reset(const MachineInstr &MI, const LiveRegSet *LiveRegsCopy,
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bool After);
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public:
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// live regs for the current state
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const decltype(LiveRegs) &getLiveRegs() const { return LiveRegs; }
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const MachineInstr *getLastTrackedMI() const { return LastTrackedMI; }
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void clearMaxPressure() { MaxPressure.clear(); }
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// returns MaxPressure, resetting it
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decltype(MaxPressure) moveMaxPressure() {
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auto Res = MaxPressure;
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MaxPressure.clear();
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return Res;
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}
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decltype(LiveRegs) moveLiveRegs() {
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return std::move(LiveRegs);
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}
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static void printLiveRegs(raw_ostream &OS, const LiveRegSet& LiveRegs,
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const MachineRegisterInfo &MRI);
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};
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class GCNUpwardRPTracker : public GCNRPTracker {
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public:
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GCNUpwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
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// reset tracker to the point just below MI
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// filling live regs upon this point using LIS
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void reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
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// move to the state just above the MI
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void recede(const MachineInstr &MI);
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// checks whether the tracker's state after receding MI corresponds
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// to reported by LIS
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bool isValid() const;
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};
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class GCNDownwardRPTracker : public GCNRPTracker {
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// Last position of reset or advanceBeforeNext
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MachineBasicBlock::const_iterator NextMI;
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MachineBasicBlock::const_iterator MBBEnd;
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public:
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GCNDownwardRPTracker(const LiveIntervals &LIS_) : GCNRPTracker(LIS_) {}
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const MachineBasicBlock::const_iterator getNext() const { return NextMI; }
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// Reset tracker to the point before the MI
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// filling live regs upon this point using LIS.
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// Returns false if block is empty except debug values.
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bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs = nullptr);
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// Move to the state right before the next MI. Returns false if reached
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// end of the block.
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bool advanceBeforeNext();
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// Move to the state at the MI, advanceBeforeNext has to be called first.
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void advanceToNext();
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// Move to the state at the next MI. Returns false if reached end of block.
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bool advance();
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// Advance instructions until before End.
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bool advance(MachineBasicBlock::const_iterator End);
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// Reset to Begin and advance to End.
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bool advance(MachineBasicBlock::const_iterator Begin,
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MachineBasicBlock::const_iterator End,
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const LiveRegSet *LiveRegsCopy = nullptr);
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};
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LaneBitmask getLiveLaneMask(unsigned Reg,
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SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI);
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GCNRPTracker::LiveRegSet getLiveRegs(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI);
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/// creates a map MachineInstr -> LiveRegSet
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/// R - range of iterators on instructions
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/// After - upon entry or exit of every instruction
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/// Note: there is no entry in the map for instructions with empty live reg set
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/// Complexity = O(NumVirtRegs * averageLiveRangeSegmentsPerReg * lg(R))
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template <typename Range>
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DenseMap<MachineInstr*, GCNRPTracker::LiveRegSet>
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getLiveRegMap(Range &&R, bool After, LiveIntervals &LIS) {
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std::vector<SlotIndex> Indexes;
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Indexes.reserve(std::distance(R.begin(), R.end()));
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auto &SII = *LIS.getSlotIndexes();
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for (MachineInstr *I : R) {
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auto SI = SII.getInstructionIndex(*I);
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Indexes.push_back(After ? SI.getDeadSlot() : SI.getBaseIndex());
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}
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llvm::sort(Indexes);
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auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
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DenseMap<MachineInstr *, GCNRPTracker::LiveRegSet> LiveRegMap;
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SmallVector<SlotIndex, 32> LiveIdxs, SRLiveIdxs;
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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auto Reg = Register::index2VirtReg(I);
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if (!LIS.hasInterval(Reg))
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continue;
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auto &LI = LIS.getInterval(Reg);
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LiveIdxs.clear();
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if (!LI.findIndexesLiveAt(Indexes, std::back_inserter(LiveIdxs)))
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continue;
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if (!LI.hasSubRanges()) {
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for (auto SI : LiveIdxs)
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LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] =
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MRI.getMaxLaneMaskForVReg(Reg);
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} else
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for (const auto &S : LI.subranges()) {
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// constrain search for subranges by indexes live at main range
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SRLiveIdxs.clear();
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S.findIndexesLiveAt(LiveIdxs, std::back_inserter(SRLiveIdxs));
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for (auto SI : SRLiveIdxs)
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LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;
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}
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}
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return LiveRegMap;
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}
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inline GCNRPTracker::LiveRegSet getLiveRegsAfter(const MachineInstr &MI,
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const LiveIntervals &LIS) {
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return getLiveRegs(LIS.getInstructionIndex(MI).getDeadSlot(), LIS,
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MI.getParent()->getParent()->getRegInfo());
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}
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inline GCNRPTracker::LiveRegSet getLiveRegsBefore(const MachineInstr &MI,
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const LiveIntervals &LIS) {
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return getLiveRegs(LIS.getInstructionIndex(MI).getBaseIndex(), LIS,
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MI.getParent()->getParent()->getRegInfo());
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}
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template <typename Range>
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GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
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Range &&LiveRegs) {
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GCNRegPressure Res;
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for (const auto &RM : LiveRegs)
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Res.inc(RM.first, LaneBitmask::getNone(), RM.second, MRI);
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return Res;
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}
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bool isEqual(const GCNRPTracker::LiveRegSet &S1,
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const GCNRPTracker::LiveRegSet &S2);
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void printLivesAt(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI);
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H
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