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73014520d6
For now, we just reschedule instructions that use the copied vregs and let regalloc elliminate it. I would really like to eliminate the copies on-the-fly during scheduling, but we need a complete implementation of repairIntervalsInRange() first. The general strategy is for the register coalescer to eliminate as many global copies as possible and shrink live ranges to be extended-basic-block local. The coalescer should not have to worry about resolving local copies (e.g. it shouldn't attemp to reorder instructions). The scheduler is a much better place to deal with local interference. The coalescer side of this equation needs work. llvm-svn: 180193
31 lines
1.2 KiB
LLVM
31 lines
1.2 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; Loop counter copies should be eliminated.
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; There is also a MUL here, but we don't care where it is scheduled.
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; CHECK: postinc
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; CHECK: *** Final schedule for BB#2 ***
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; CHECK: t2LDRs
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; CHECK: t2ADDrr
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; CHECK: t2CMPrr
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; CHECK: COPY
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define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind {
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entry:
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%cmp4 = icmp eq i32 %a, 0
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br i1 %cmp4, label %for.end, label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ]
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%indvars.iv.next = add i32 %indvars.iv, %s
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%arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv
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%0 = load i32* %arrayidx, align 4
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%mul = mul nsw i32 %0, %s.05
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%exitcond = icmp eq i32 %indvars.iv.next, %a
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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%s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
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ret i32 %s.0.lcssa
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}
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