mirror of
https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
533 lines
15 KiB
LLVM
533 lines
15 KiB
LLVM
; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
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; RUN: llc < %s -march=arm64 | FileCheck %s
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%struct.X = type { i8, i8, [2 x i8] }
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%struct.Y = type { i32, i8 }
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%struct.Z = type { i8, i8, [2 x i8], i16 }
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%struct.A = type { i64, i8 }
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define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp {
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; CHECK-LABEL: foo:
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; CHECK: ubfx
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; CHECK-NOT: and
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; CHECK: ret
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%tmp = bitcast %struct.X* %x to i32*
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%tmp1 = load i32* %tmp, align 4
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%b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1
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%bf.clear = lshr i32 %tmp1, 3
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%bf.clear.lobit = and i32 %bf.clear, 1
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%frombool = trunc i32 %bf.clear.lobit to i8
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store i8 %frombool, i8* %b, align 1
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ret void
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}
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define i32 @baz(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: baz:
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; CHECK: sbfx w0, w0, #0, #4
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%tmp = trunc i64 %cav1.coerce to i32
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%tmp1 = shl i32 %tmp, 28
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%bf.val.sext = ashr exact i32 %tmp1, 28
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ret i32 %bf.val.sext
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}
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define i32 @bar(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: sbfx w0, w0, #4, #6
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%tmp = trunc i64 %cav1.coerce to i32
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%cav1.sroa.0.1.insert = shl i32 %tmp, 22
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%tmp1 = ashr i32 %cav1.sroa.0.1.insert, 26
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ret i32 %tmp1
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}
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define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind optsize ssp {
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; CHECK-LABEL: fct1:
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; CHECK: ubfx
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; CHECK-NOT: and
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; CHECK: ret
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%tmp = bitcast %struct.Z* %x to i64*
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%tmp1 = load i64* %tmp, align 4
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%b = getelementptr inbounds %struct.A* %y, i64 0, i32 0
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%bf.clear = lshr i64 %tmp1, 3
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%bf.clear.lobit = and i64 %bf.clear, 1
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store i64 %bf.clear.lobit, i64* %b, align 8
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ret void
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}
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define i64 @fct2(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: fct2:
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; CHECK: sbfx x0, x0, #0, #36
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%tmp = shl i64 %cav1.coerce, 28
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%bf.val.sext = ashr exact i64 %tmp, 28
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ret i64 %bf.val.sext
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}
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define i64 @fct3(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: fct3:
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; CHECK: sbfx x0, x0, #4, #38
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%cav1.sroa.0.1.insert = shl i64 %cav1.coerce, 22
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%tmp1 = ashr i64 %cav1.sroa.0.1.insert, 26
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ret i64 %tmp1
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}
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define void @fct4(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct4:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24
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; CHECK-NEXT: str [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -16777216
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 16777215
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%or = or i64 %and, %and1
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store i64 %or, i64* %y, align 8
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ret void
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}
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define void @fct5(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct5:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
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; CHECK-NEXT: str [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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store i32 %or, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some low bits
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define void @fct6(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct6:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shr1 = lshr i32 %or, 2
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store i32 %shr1, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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define void @fct7(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct7:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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store i32 %shl, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some low bits
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; (i64 version)
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define void @fct8(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct8:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shr1 = lshr i64 %or, 2
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store i64 %shr1, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; (i64 version)
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define void @fct9(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct9:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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store i64 %shl, i64* %y, align 8
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ret void
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}
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; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
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; (i32 version)
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define void @fct10(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct10:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #0, #3
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%and1 = and i32 %x, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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store i32 %shl, i32* %y, align 8
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ret void
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}
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; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
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; (i64 version)
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define void @fct11(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct11:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #0, #3
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%and1 = and i64 %x, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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store i64 %shl, i64* %y, align 8
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ret void
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}
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define zeroext i1 @fct12bis(i32 %tmp2) unnamed_addr nounwind ssp align 2 {
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; CHECK-LABEL: fct12bis:
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; CHECK-NOT: and
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; CHECK: ubfx w0, w0, #11, #1
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%and.i.i = and i32 %tmp2, 2048
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%tobool.i.i = icmp ne i32 %and.i.i, 0
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ret i1 %tobool.i.i
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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define void @fct12(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct12:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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%shr2 = lshr i32 %shl, 4
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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; (i64 version)
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define void @fct13(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct13:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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%shr2 = lshr i64 %shl, 4
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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define void @fct14(i32* nocapture %y, i32 %x, i32 %x1) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct14:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], w1, #16, #8
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #4
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; CHECK-NEXT: bfxil [[REG2]], w2, #5, #3
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -256
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 255
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%or = or i32 %and, %and1
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%shl = lshr i32 %or, 4
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%and2 = and i32 %shl, -8
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%shr1 = lshr i32 %x1, 5
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%and3 = and i32 %shr1, 7
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%or1 = or i32 %and2, %and3
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%shl1 = shl i32 %or1, 2
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store i32 %shl1, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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; (i64 version)
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define void @fct15(i64* nocapture %y, i64 %x, i64 %x1) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct15:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfxil [[REG1]], x1, #16, #8
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #4
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; CHECK-NEXT: bfxil [[REG2]], x2, #5, #3
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -256
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 255
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%or = or i64 %and, %and1
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%shl = lshr i64 %or, 4
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%and2 = and i64 %shl, -8
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%shr1 = lshr i64 %x1, 5
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%and3 = and i64 %shr1, 7
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%or1 = or i64 %and2, %and3
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%shl1 = shl i64 %or1, 2
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store i64 %shl1, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits and a masking operation has to be kept
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define void @fct16(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct16:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; Create the constant
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; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16
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; CHECK: movk [[REGCST]], #0x8160
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; Do the masking
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; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
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; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, 1737056
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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%shr2 = lshr i32 %shl, 4
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits and a masking operation has to be kept
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; (i64 version)
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define void @fct17(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct17:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; Create the constant
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; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16
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; CHECK: movk w[[REGCST]], #0x8160
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; Do the masking
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; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
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; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, 1737056
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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%shr2 = lshr i64 %shl, 4
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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define i64 @fct18(i32 %xor72) nounwind ssp {
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; CHECK-LABEL: fct18:
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; CHECK: ubfx x0, x0, #9, #8
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%shr81 = lshr i32 %xor72, 9
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%conv82 = zext i32 %shr81 to i64
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%result = and i64 %conv82, 255
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ret i64 %result
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}
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; Using the access to the global array to keep the instruction and control flow.
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@first_ones = external global [65536 x i8]
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; Function Attrs: nounwind readonly ssp
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define i32 @fct19(i64 %arg1) nounwind readonly ssp {
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; CHECK-LABEL: fct19:
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entry:
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%x.sroa.1.0.extract.shift = lshr i64 %arg1, 16
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%x.sroa.1.0.extract.trunc = trunc i64 %x.sroa.1.0.extract.shift to i16
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%x.sroa.3.0.extract.shift = lshr i64 %arg1, 32
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%x.sroa.5.0.extract.shift = lshr i64 %arg1, 48
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%tobool = icmp eq i64 %x.sroa.5.0.extract.shift, 0
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br i1 %tobool, label %if.end, label %if.then
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if.then: ; preds = %entry
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%arrayidx3 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift
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%0 = load i8* %arrayidx3, align 1
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%conv = zext i8 %0 to i32
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br label %return
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; OPT-LABEL: if.end
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if.end: ; preds = %entry
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; OPT: lshr
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; CHECK: ubfx [[REG1:x[0-9]+]], [[REG2:x[0-9]+]], #32, #16
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%x.sroa.3.0.extract.trunc = trunc i64 %x.sroa.3.0.extract.shift to i16
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%tobool6 = icmp eq i16 %x.sroa.3.0.extract.trunc, 0
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; CHECK: cbz
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br i1 %tobool6, label %if.end13, label %if.then7
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; OPT-LABEL: if.then7
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if.then7: ; preds = %if.end
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; OPT: lshr
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; "and" should be combined to "ubfm" while "ubfm" should be removed by cse.
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; So neither of them should be in the assemble code.
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; CHECK-NOT: and
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; CHECK-NOT: ubfm
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%idxprom10 = and i64 %x.sroa.3.0.extract.shift, 65535
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%arrayidx11 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom10
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%1 = load i8* %arrayidx11, align 1
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%conv12 = zext i8 %1 to i32
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%add = add nsw i32 %conv12, 16
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br label %return
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; OPT-LABEL: if.end13
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if.end13: ; preds = %if.end
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; OPT: lshr
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; OPT: trunc
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; CHECK: ubfx [[REG3:x[0-9]+]], [[REG4:x[0-9]+]], #16, #16
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%tobool16 = icmp eq i16 %x.sroa.1.0.extract.trunc, 0
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; CHECK: cbz
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br i1 %tobool16, label %return, label %if.then17
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; OPT-LABEL: if.then17
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if.then17: ; preds = %if.end13
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; OPT: lshr
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; "and" should be combined to "ubfm" while "ubfm" should be removed by cse.
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; So neither of them should be in the assemble code.
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; CHECK-NOT: and
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; CHECK-NOT: ubfm
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%idxprom20 = and i64 %x.sroa.1.0.extract.shift, 65535
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%arrayidx21 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom20
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%2 = load i8* %arrayidx21, align 1
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%conv22 = zext i8 %2 to i32
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%add23 = add nsw i32 %conv22, 32
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br label %return
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return: ; preds = %if.end13, %if.then17, %if.then7, %if.then
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; CHECK: ret
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%retval.0 = phi i32 [ %conv, %if.then ], [ %add, %if.then7 ], [ %add23, %if.then17 ], [ 64, %if.end13 ]
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ret i32 %retval.0
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}
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; Make sure we do not assert if the immediate in and is bigger than i64.
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; PR19503.
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; OPT-LABEL: @fct20
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; OPT: lshr
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; OPT-NOT: lshr
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; OPT: ret
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; CHECK-LABEL: fct20:
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; CHECK: ret
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define i80 @fct20(i128 %a, i128 %b) {
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entry:
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%shr = lshr i128 %a, 18
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%conv = trunc i128 %shr to i80
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%tobool = icmp eq i128 %b, 0
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br i1 %tobool, label %then, label %end
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then:
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%and = and i128 %shr, 483673642326615442599424
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%conv2 = trunc i128 %and to i80
|
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br label %end
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end:
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%conv3 = phi i80 [%conv, %entry], [%conv2, %then]
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ret i80 %conv3
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}
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; Check if we can still catch UBFX when "AND" is used by SHL.
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; CHECK-LABEL: fct21:
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; CHECK: ubfx
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@arr = external global [8 x [64 x i64]]
|
|
define i64 @fct21(i64 %x) {
|
|
entry:
|
|
%shr = lshr i64 %x, 4
|
|
%and = and i64 %shr, 15
|
|
%arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and
|
|
%0 = load i64* %arrayidx, align 8
|
|
ret i64 %0
|
|
}
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|
|
|
define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
|
|
; CHECK-LABEL: test_ignored_rightbits:
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|
|
|
%positioned_field = shl i32 %in, 3
|
|
%positioned_masked_field = and i32 %positioned_field, 120
|
|
%masked_dst = and i32 %dst, 7
|
|
%insertion = or i32 %masked_dst, %positioned_masked_field
|
|
; CHECK: {{bfm|bfi|bfxil}}
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|
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%shl16 = shl i32 %insertion, 8
|
|
%or18 = or i32 %shl16, %insertion
|
|
%conv19 = trunc i32 %or18 to i16
|
|
; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #8, #7
|
|
|
|
ret i16 %conv19
|
|
}
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