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dd6e5e3f62
Add support for the last two missing fcmp condition codes: UEQ and ONE. This fixes rdar://problem/18341575. llvm-svn: 217823
163 lines
3.7 KiB
LLVM
163 lines
3.7 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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define zeroext i1 @fcmp_float1(float %a) {
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; CHECK-LABEL: fcmp_float1
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; CHECK: fcmp s0, #0.0
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @fcmp_float2(float %a, float %b) {
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; CHECK-LABEL: fcmp_float2
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_double1(double %a) {
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; CHECK-LABEL: fcmp_double1
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; CHECK: fcmp d0, #0.0
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une double %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @fcmp_double2(double %a, double %b) {
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; CHECK-LABEL: fcmp_double2
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; CHECK: fcmp d0, d1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une double %a, %b
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ret i1 %1
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}
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; Check each fcmp condition
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define zeroext i1 @fcmp_false(float %a) {
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; CHECK-LABEL: fcmp_false
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; CHECK: mov {{w[0-9]+}}, wzr
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%1 = fcmp ogt float %a, %a
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ret i1 %1
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}
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define zeroext i1 @fcmp_oeq(float %a, float %b) {
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; CHECK-LABEL: fcmp_oeq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, eq
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%1 = fcmp oeq float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ogt(float %a, float %b) {
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; CHECK-LABEL: fcmp_ogt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, gt
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%1 = fcmp ogt float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_oge(float %a, float %b) {
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; CHECK-LABEL: fcmp_oge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ge
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%1 = fcmp oge float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_olt(float %a, float %b) {
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; CHECK-LABEL: fcmp_olt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, mi
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%1 = fcmp olt float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ole(float %a, float %b) {
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; CHECK-LABEL: fcmp_ole
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ls
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%1 = fcmp ole float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_one(float %a, float %b) {
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; CHECK-LABEL: fcmp_one
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset [[REG:w[0-9]+]], mi
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; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, le
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%1 = fcmp one float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ord(float %a, float %b) {
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; CHECK-LABEL: fcmp_ord
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, vc
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%1 = fcmp ord float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_uno(float %a, float %b) {
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; CHECK-LABEL: fcmp_uno
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, vs
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%1 = fcmp uno float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ueq(float %a, float %b) {
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; CHECK-LABEL: fcmp_ueq
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
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; CHECK-NEXT: csinc {{w[0-9]+}}, [[REG]], wzr, vc
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%1 = fcmp ueq float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ugt(float %a, float %b) {
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; CHECK-LABEL: fcmp_ugt
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, hi
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%1 = fcmp ugt float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_uge(float %a, float %b) {
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; CHECK-LABEL: fcmp_uge
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, pl
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%1 = fcmp uge float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ult(float %a, float %b) {
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; CHECK-LABEL: fcmp_ult
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, lt
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%1 = fcmp ult float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_ule(float %a, float %b) {
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; CHECK-LABEL: fcmp_ule
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, le
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%1 = fcmp ule float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_une(float %a, float %b) {
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; CHECK-LABEL: fcmp_une
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; CHECK: fcmp s0, s1
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; CHECK-NEXT: cset {{w[0-9]+}}, ne
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%1 = fcmp une float %a, %b
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ret i1 %1
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}
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define zeroext i1 @fcmp_true(float %a) {
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; CHECK-LABEL: fcmp_true
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; CHECK: orr {{w[0-9]+}}, wzr, #0x1
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%1 = fcmp ueq float %a, %a
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ret i1 %1
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}
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