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llvm-mirror/test/CodeGen/AArch64/fast-isel-gep.ll
Juergen Ributzka fb67fff9cb [FastISel][AArch64] Don't bail during simple GEP instruction selection.
The generic FastISel code would bail, because it can't emit a sign-extend for
AArch64. This copies the code over and uses AArch64 specific emit functions.

This is not ideal and 'computeAddress' should handles this, so it can fold the
address computation into the memory operation.

I plan to clean up 'computeAddress' anyways, so I will add that in a future
commit.

Related to rdar://problem/18962471.

llvm-svn: 221923
2014-11-13 20:50:44 +00:00

50 lines
1.3 KiB
LLVM

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
%struct.foo = type { i32, i64, float, double }
define double* @test_struct(%struct.foo* %f) {
; CHECK-LABEL: test_struct
; CHECK: add x0, x0, #24
%1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3
ret double* %1
}
define i32* @test_array1(i32* %a, i64 %i) {
; CHECK-LABEL: test_array1
; CHECK: orr [[REG:x[0-9]+]], xzr, #0x4
; CHECK-NEXT: madd x0, x1, [[REG]], x0
%1 = getelementptr inbounds i32* %a, i64 %i
ret i32* %1
}
define i32* @test_array2(i32* %a) {
; CHECK-LABEL: test_array2
; CHECK: add x0, x0, #16
%1 = getelementptr inbounds i32* %a, i64 4
ret i32* %1
}
define i32* @test_array3(i32* %a) {
; CHECK-LABEL: test_array3
; CHECK: add x0, x0, #1, lsl #12
%1 = getelementptr inbounds i32* %a, i64 1024
ret i32* %1
}
define i32* @test_array4(i32* %a) {
; CHECK-LABEL: test_array4
; CHECK: movz [[REG:x[0-9]+]], #0x1008
; CHECK-NEXR: add x0, x0, [[REG]]
%1 = getelementptr inbounds i32* %a, i64 1026
ret i32* %1
}
define i32* @test_array5(i32* %a, i32 %i) {
; CHECK-LABEL: test_array5
; CHECK: sxtw [[REG1:x[0-9]+]], w1
; CHECK-NEXT: orr [[REG2:x[0-9]+]], xzr, #0x4
; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
%1 = getelementptr inbounds i32* %a, i32 %i
ret i32* %1
}