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52c4471b99
Summary: mark G_LOAD/G_STORE vec256/512 legal for AVX/AVX512. Implement instruction selection. Reviewers: zvi, guyblank Reviewed By: zvi Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33268 llvm-svn: 303617
50 lines
1.5 KiB
C++
50 lines
1.5 KiB
C++
//===- X86LegalizerInfo.h ------------------------------------------*- C++
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//-*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for X86.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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namespace llvm {
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class X86Subtarget;
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class X86TargetMachine;
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/// This class provides the information for the target register banks.
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class X86LegalizerInfo : public LegalizerInfo {
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private:
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/// Keep a reference to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget &Subtarget;
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const X86TargetMachine &TM;
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public:
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X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
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private:
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void setLegalizerInfo32bit();
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void setLegalizerInfo64bit();
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void setLegalizerInfoSSE1();
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void setLegalizerInfoSSE2();
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void setLegalizerInfoSSE41();
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void setLegalizerInfoAVX();
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void setLegalizerInfoAVX2();
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void setLegalizerInfoAVX512();
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void setLegalizerInfoAVX512DQ();
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void setLegalizerInfoAVX512BW();
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};
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} // namespace llvm
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#endif
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