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llvm-mirror/test/DebugInfo/MIR
Jeremy Morse d7cf7abb78 [DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes
This is a cleanup patch -- we're now able to support all flavours of
variable location in instruction referencing mode. This patch updates
various tests for debug instructions to be broader: numerous code paths
try to ignore debug isntructions, and they now have to ignore the
additional DBG_PHI and DBG_INSTR_REFs that we can generate.

A small amount of rework happens for LiveDebugVariables: as we don't need
to track live intervals through regalloc any more, we can get away with
unlinking debug instructions before regalloc, then re-inserting them after.
Note that this isn't (yet) true of DBG_VALUE_LISTs, they still have to go
through live interval tracking.

In SelectionDAG, add a helper lambda that emits half-formed DBG_INSTR_REFs
for arguments in instr-ref mode, DBG_VALUE otherwise. This is one of the
final locations where DBG_VALUEs are emitted for vreg arguments.

X86InstrInfo now un-sets the debug instr number on SUB instructions that
get mutated into CMP instructions. As the instruction no longer computes a
subtraction, we can't use it for variable locations.

Differential Revision: https://reviews.llvm.org/D88898
2021-07-08 16:42:24 +01:00
..
AArch64 CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ARM CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Hexagon [LiveDebugValues][InstrRef][2/2] Emit entry value variable locations 2021-06-30 23:07:39 +01:00
InstrRef [DebugInfo][InstrRef][4/4] Support DBG_INSTR_REF through all backend passes 2021-07-08 16:42:24 +01:00
Mips CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
SystemZ [SystemZ] Separate LoZ ELF specifics in tablegen. 2021-02-17 16:11:58 -05:00
X86 [LiveDebugValues][InstrRef][2/2] Emit entry value variable locations 2021-06-30 23:07:39 +01:00
lit.local.cfg