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d847d985b9
Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
42 lines
1.9 KiB
LLVM
42 lines
1.9 KiB
LLVM
; Test all important variants of the unconditional 'br' instruction.
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; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6C
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; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
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; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
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define i32 @br(i8 *%addr) {
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; ALL-LABEL: br:
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; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
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; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC
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; ALL: $BB0_1: # %L1
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
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; ALL: addiu $2, $zero, 0
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; ALL: $BB0_2: # %L2
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; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
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; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
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; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
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; ALL: addiu $2, $zero, 1
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entry:
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indirectbr i8* %addr, [label %L1, label %L2]
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L1:
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ret i32 0
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L2:
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ret i32 1
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}
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