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3fdcf4e64c
If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs!
Motivating testcase:
void f(float *a, float *b, float *c, int n) {
while (n-- > 0)
*c++ = *a++ + *b++;
}
It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage.
llvm-svn: 278658
43 lines
1.1 KiB
LLVM
43 lines
1.1 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 | FileCheck %s
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; subs r4, #1
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; cmp r4, 0
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; bgt
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; cmp cannot be optimized away since it will clear the overflow bit.
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; gt / ge, lt, le conditions all depend on V bit.
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; rdar://9172742
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define i32 @t() nounwind {
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; CHECK-LABEL: t:
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entry:
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br label %bb2
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bb: ; preds = %bb2
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%0 = tail call i32 @rand() nounwind
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%1 = icmp eq i32 %0, 50
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br i1 %1, label %bb3, label %bb1
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bb1: ; preds = %bb
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; CHECK: bb1
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; CHECK: subs [[REG:r[0-9]+]], #1
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%tmp = tail call i32 @puts() nounwind
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%indvar.next = add i32 %indvar, 1
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br label %bb2
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bb2: ; preds = %bb1, %entry
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; CHECK: bb2
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; CHECK: cmp [[REG]], #0
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; CHECK: ble
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
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%tries.0 = sub i32 2147483647, %indvar
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%tmp1 = icmp sgt i32 %tries.0, 0
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br i1 %tmp1, label %bb, label %bb3
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bb3: ; preds = %bb2, %bb
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ret i32 0
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}
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declare i32 @rand()
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declare i32 @puts() nounwind
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