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e0603b95db
This patch adds lowering for atomic fences and relies on AtomicExpandPass to lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls. test/CodeGen/RISCV/atomic-* are modelled on the exhaustive test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A codegen support is introduced. Fence mappings are taken from table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Differential Revision: https://reviews.llvm.org/D47587 llvm-svn: 334590
42 lines
985 B
LLVM
42 lines
985 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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define void @fence_acquire() nounwind {
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; RV32I-LABEL: fence_acquire:
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; RV32I: # %bb.0:
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; RV32I-NEXT: fence r, rw
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; RV32I-NEXT: ret
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fence acquire
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ret void
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}
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define void @fence_release() nounwind {
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; RV32I-LABEL: fence_release:
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; RV32I: # %bb.0:
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; RV32I-NEXT: fence rw, w
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; RV32I-NEXT: ret
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fence release
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ret void
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}
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define void @fence_acq_rel() nounwind {
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; RV32I-LABEL: fence_acq_rel:
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; RV32I: # %bb.0:
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; RV32I-NEXT: fence.tso
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; RV32I-NEXT: ret
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fence acq_rel
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ret void
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}
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define void @fence_seq_cst() nounwind {
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; RV32I-LABEL: fence_seq_cst:
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; RV32I: # %bb.0:
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; RV32I-NEXT: fence rw, rw
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; RV32I-NEXT: ret
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fence seq_cst
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ret void
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}
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