mirror of
https://github.com/RPCS3/llvm-mirror.git
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59c2440372
This change renames the intrinsics to not have "experimental" in the name. The autoupgrader will handle legacy intrinsics. Relevant ML thread: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140729.html Differential Revision: https://reviews.llvm.org/D88787
131 lines
4.5 KiB
LLVM
131 lines
4.5 KiB
LLVM
; RUN: opt -S < %s | FileCheck %s
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; RUN: llvm-dis < %s.bc | FileCheck %s
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define float @fadd_v2(<4 x float> %in, float %acc) {
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; CHECK-LABEL: @fadd_v2
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; CHECK: %res = call float @llvm.vector.reduce.fadd.v4f32(float %acc, <4 x float> %in)
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%res = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %acc, <4 x float> %in)
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ret float %res
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}
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define float @fadd_v2_fast(<4 x float> %in, float %acc) {
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; CHECK-LABEL: @fadd_v2_fast
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; CHECK: %res = call fast float @llvm.vector.reduce.fadd.v4f32(float %acc, <4 x float> %in)
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%res = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float %acc, <4 x float> %in)
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ret float %res
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}
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define float @fmul_v2(<4 x float> %in, float %acc) {
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; CHECK-LABEL: @fmul_v2
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; CHECK: %res = call float @llvm.vector.reduce.fmul.v4f32(float %acc, <4 x float> %in)
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%res = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %acc, <4 x float> %in)
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ret float %res
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}
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define float @fmul_v2_fast(<4 x float> %in, float %acc) {
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; CHECK-LABEL: @fmul_v2_fast
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; CHECK: %res = call fast float @llvm.vector.reduce.fmul.v4f32(float %acc, <4 x float> %in)
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%res = call fast float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float %acc, <4 x float> %in)
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ret float %res
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}
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define float @fmin(<4 x float> %in) {
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; CHECK-LABEL: @fmin
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; CHECK: %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %in)
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%res = call float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float> %in)
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ret float %res
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}
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define float @fmax(<4 x float> %in) {
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; CHECK-LABEL: @fmax
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; CHECK: %res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %in)
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%res = call float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float> %in)
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ret float %res
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}
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define i32 @and(<4 x i32> %in) {
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; CHECK-LABEL: @and
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; CHECK: %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @or(<4 x i32> %in) {
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; CHECK-LABEL: @or
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; CHECK: %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @xor(<4 x i32> %in) {
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; CHECK-LABEL: @xor
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; CHECK: %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @smin(<4 x i32> %in) {
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; CHECK-LABEL: @smin
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; CHECK: %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @smax(<4 x i32> %in) {
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; CHECK-LABEL: @smax
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; CHECK: %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @umin(<4 x i32> %in) {
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; CHECK-LABEL: @umin
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; CHECK: %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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define i32 @umax(<4 x i32> %in) {
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; CHECK-LABEL: @umax
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; CHECK: %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %in)
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%res = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %in)
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ret i32 %res
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}
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declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x float>)
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declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v4f32(float, <4 x float>)
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declare float @llvm.experimental.vector.reduce.fmin.v4f32(<4 x float>)
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; CHECK: declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
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declare float @llvm.experimental.vector.reduce.fmax.v4f32(<4 x float>)
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; CHECK: declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
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declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
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declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
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; CHECK: declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)
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