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f90261141b
Reverts "[X86] Remove (V)MOV64toSDrr/m and (V)MOVDI2SSrr/m. Use 128-bit result MOVD/MOVQ and COPY_TO_REGCLASS instead" Reverts "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling" Eric Christopher and Jorge Gorbe Moya reported some issues with these patches to me off list. Removing the CodeGenOnly instructions has changed how fneg is handled during fast-isel with sse/sse2. We're now emitting fsub -0.0, x instead moving to the integer domain(in a GPR), xoring the sign bit, and then moving back to xmm. This is because the fast isel table no longer contains an entry for (f32/f64 bitcast (i32/i64)) so the target independent fneg code fails. The use of fsub changes the behavior of nan with respect to -O2 codegen which will always use a pxor. NOTE: We still have a difference with double with -m32 since the move to GPR doesn't work there. I'll file a separate PR for that and add test cases. Since removing the CodeGenOnly instructions was fixing PR41619, I'm reverting r358887 which exposed that PR. Though I wouldn't be surprised if that bug can still be hit independent of that. This should hopefully get Google back to green. I'll work with Simon and other X86 folks to figure out how to move forward again. llvm-svn: 360066
41 lines
988 B
YAML
41 lines
988 B
YAML
# RUN: llc -mtriple=x86_64-- -run-pass=peephole-opt %s -o - | FileCheck %s
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--- |
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define void @func() { ret void }
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...
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---
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# Check that instructions with MI.isBitcast() are only replaced by COPY if there
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# are no SUBREG_TO_REG users.
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# CHECK-LABEL: name: func
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name: func
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: fr32 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr32 }
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- { id: 4, class: fr32 }
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- { id: 5, class: gr32 }
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- { id: 6, class: gr64 }
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body: |
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bb.0:
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; CHECK: %1:fr32 = VMOVDI2SSrr %0
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; CHECK: %7:gr32 = COPY %0
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; CHECK: NOOP implicit %7
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%0 = MOV32ri 42
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%1 = VMOVDI2SSrr %0
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%2 = MOVSS2DIrr %1
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NOOP implicit %2
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; CHECK: %4:fr32 = VMOVDI2SSrr %3
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; CHECK-NOT: COPY
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; CHECK: %5:gr32 = MOVSS2DIrr %4
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; CHECK: %6:gr64 = SUBREG_TO_REG %5, 0
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; CHECK: NOOP implicit %6
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%3 = MOV32ri 42
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%4 = VMOVDI2SSrr %3
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%5 = MOVSS2DIrr %4
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%6 = SUBREG_TO_REG %5, 0, %subreg.sub_32bit
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NOOP implicit %6
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...
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