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ead0e16c6e
This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
69 lines
2.4 KiB
C++
69 lines
2.4 KiB
C++
//===-- WebAssemblyRegisterInfo.cpp - WebAssembly Register Information ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file contains the WebAssembly implementation of the
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/// TargetRegisterInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyRegisterInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyFrameLowering.h"
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#include "WebAssemblyInstrInfo.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-reg-info"
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#define GET_REGINFO_TARGET_DESC
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#include "WebAssemblyGenRegisterInfo.inc"
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WebAssemblyRegisterInfo::WebAssemblyRegisterInfo(const Triple &TT)
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: WebAssemblyGenRegisterInfo(0), TT(TT) {}
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const MCPhysReg *
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WebAssemblyRegisterInfo::getCalleeSavedRegs(const MachineFunction *) const {
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static const MCPhysReg CalleeSavedRegs[] = {0};
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return CalleeSavedRegs;
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}
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BitVector
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WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
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WebAssembly::FP64})
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Reserved.set(Reg);
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return Reserved;
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}
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void WebAssemblyRegisterInfo::eliminateFrameIndex(
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MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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llvm_unreachable("WebAssemblyRegisterInfo::eliminateFrameIndex"); // FIXME
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}
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unsigned
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WebAssemblyRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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static const unsigned Regs[2][2] = {
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/* !isArch64Bit isArch64Bit */
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/* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64},
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/* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
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const WebAssemblyFrameLowering *TFI = getFrameLowering(MF);
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return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
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}
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