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df40ece177
Re-land r321234. It had to be reverted because it broke the shared library build. The shared library build broke because there was a missing LLVMBuild dependency from lib/Passes (which calls TargetMachine::getTargetIRAnalysis) to lib/Target. As far as I can tell, this problem was always there but was somehow masked before (perhaps because TargetMachine::getTargetIRAnalysis was a virtual function). Original commit message: This makes the TargetMachine interface a bit simpler. We still need the std::function in TargetIRAnalysis to avoid having to add a dependency from Analysis to Target. See discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html I avoided adding all of the backend owners to this review since the change is simple, but let me know if you feel differently about this. Reviewers: echristo, MatzeB, hfinkel Reviewed By: hfinkel Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D41464 llvm-svn: 321375
288 lines
11 KiB
C++
288 lines
11 KiB
C++
//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Mips target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetMachine.h"
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#include "MCTargetDesc/MipsABIInfo.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "Mips.h"
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#include "Mips16ISelDAGToDAG.h"
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#include "MipsSEISelDAGToDAG.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetObjectFile.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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#include <string>
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using namespace llvm;
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#define DEBUG_TYPE "mips"
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extern "C" void LLVMInitializeMipsTarget() {
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// Register the target.
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RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
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RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
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RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
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RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
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}
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static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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const TargetOptions &Options,
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bool isLittle) {
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std::string Ret;
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MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
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// There are both little and big endian mips.
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if (isLittle)
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Ret += "e";
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else
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Ret += "E";
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if (ABI.IsO32())
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Ret += "-m:m";
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else
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Ret += "-m:e";
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// Pointers are 32 bit on some ABIs.
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if (!ABI.IsN64())
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Ret += "-p:32:32";
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// 8 and 16 bit integers only need to have natural alignment, but try to
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// align them to 32 bits. 64 bit integers have natural alignment.
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Ret += "-i8:8:32-i16:16:32-i64:64";
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// 32 bit registers are always available and the stack is at least 64 bit
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// aligned. On N64 64 bit registers are also available and the stack is
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// 128 bit aligned.
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if (ABI.IsN64() || ABI.IsN32())
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Ret += "-n32:64-S128";
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else
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Ret += "-n32-S64";
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return Ret;
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}
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static Reloc::Model getEffectiveRelocModel(bool JIT,
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Optional<Reloc::Model> RM) {
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if (!RM.hasValue() || JIT)
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return Reloc::Static;
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return *RM;
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}
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer, using StackGrowsUp enables
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// an easier handling.
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// Using CodeModel::Large enables different CALL behavior.
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MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT,
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bool isLittle)
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
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CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
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getEffectiveCodeModel(CM), OL),
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isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()),
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ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
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Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this,
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Options.StackAlignmentOverride),
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NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
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isLittle, *this, Options.StackAlignmentOverride),
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Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
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isLittle, *this, Options.StackAlignmentOverride) {
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Subtarget = &DefaultSubtarget;
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initAsmInfo();
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}
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MipsTargetMachine::~MipsTargetMachine() = default;
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void MipsebTargetMachine::anchor() {}
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MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
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void MipselTargetMachine::anchor() {}
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MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
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const MipsSubtarget *
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MipsTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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bool hasMips16Attr =
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!F.getFnAttribute("mips16").hasAttribute(Attribute::None);
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bool hasNoMips16Attr =
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!F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
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bool HasMicroMipsAttr =
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!F.getFnAttribute("micromips").hasAttribute(Attribute::None);
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bool HasNoMicroMipsAttr =
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!F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
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// FIXME: This is related to the code below to reset the target options,
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// we need to know whether or not the soft float flag is set on the
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// function, so we can enable it as a subtarget feature.
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bool softFloat =
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F.hasFnAttribute("use-soft-float") &&
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F.getFnAttribute("use-soft-float").getValueAsString() == "true";
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if (hasMips16Attr)
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FS += FS.empty() ? "+mips16" : ",+mips16";
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else if (hasNoMips16Attr)
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FS += FS.empty() ? "-mips16" : ",-mips16";
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if (HasMicroMipsAttr)
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FS += FS.empty() ? "+micromips" : ",+micromips";
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else if (HasNoMicroMipsAttr)
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FS += FS.empty() ? "-micromips" : ",-micromips";
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if (softFloat)
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FS += FS.empty() ? "+soft-float" : ",+soft-float";
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this,
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Options.StackAlignmentOverride);
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}
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return I.get();
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}
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void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
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DEBUG(dbgs() << "resetSubtarget\n");
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Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction()));
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MF->setSubtarget(Subtarget);
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}
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namespace {
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/// Mips Code Generator Pass Configuration Options.
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class MipsPassConfig : public TargetPassConfig {
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public:
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MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {
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// The current implementation of long branch pass requires a scratch
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// register ($at) to be available before branch instructions. Tail merging
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// can break this requirement, so disable it when long branch pass is
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// enabled.
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EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
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}
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MipsTargetMachine &getMipsTargetMachine() const {
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return getTM<MipsTargetMachine>();
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}
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const MipsSubtarget &getMipsSubtarget() const {
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return *getMipsTargetMachine().getSubtargetImpl();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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} // end anonymous namespace
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TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new MipsPassConfig(*this, PM);
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}
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void MipsPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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addPass(createAtomicExpandPass());
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if (getMipsSubtarget().os16())
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addPass(createMipsOs16Pass());
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if (getMipsSubtarget().inMips16HardFloat())
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addPass(createMips16HardFloatPass());
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}
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// Install an instruction selector pass using
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// the ISelDag to gen Mips code.
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bool MipsPassConfig::addInstSelector() {
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addPass(createMipsModuleISelDagPass());
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addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
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addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
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return false;
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}
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void MipsPassConfig::addPreRegAlloc() {
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addPass(createMipsOptimizePICCallPass());
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}
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TargetTransformInfo
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MipsTargetMachine::getTargetTransformInfo(const Function &F) {
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if (Subtarget->allowMixed16_32()) {
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DEBUG(errs() << "No Target Transform Info Pass Added\n");
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// FIXME: This is no longer necessary as the TTI returned is per-function.
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return TargetTransformInfo(F.getParent()->getDataLayout());
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}
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DEBUG(errs() << "Target Transform Info Pass Added\n");
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return TargetTransformInfo(BasicTTIImpl(this, F));
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}
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// Implemented by targets that want to run passes immediately before
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// machine code is emitted. return true if -print-machineinstrs should
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// print out the code after the passes.
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void MipsPassConfig::addPreEmitPass() {
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addPass(createMicroMipsSizeReductionPass());
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// The delay slot filler and the long branch passes can potientially create
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// forbidden slot/ hazards for MIPSR6 which the hazard schedule pass will
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// fix. Any new pass must come before the hazard schedule pass.
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addPass(createMipsDelaySlotFillerPass());
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addPass(createMipsLongBranchPass());
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addPass(createMipsHazardSchedule());
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addPass(createMipsConstantIslandPass());
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}
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