1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/include/llvm/Target
Jakob Stoklund Olesen 93b4cf4daf Remove extra MayLoad/MayStore flags from atomic_load/store.
These extra flags are not required to properly order the atomic
load/store instructions. SelectionDAGBuilder chains atomics as if they
were volatile, and SelectionDAG::getAtomic() sets the isVolatile bit on
the memory operands of all atomic operations.

The volatile bit is enough to order atomic loads and stores during and
after SelectionDAG.

This means we set mayLoad on atomic_load, mayStore on atomic_store, and
mayLoad+mayStore on the remaining atomic read-modify-write operations.

llvm-svn: 162733
2012-08-28 03:11:32 +00:00
..
Mangler.h
Target.td Tristate mayLoad, mayStore, and hasSideEffects. 2012-08-23 19:34:46 +00:00
TargetCallingConv.h
TargetCallingConv.td
TargetData.h Revert r161371. Removing the 'const' before Type is a "good thing". 2012-08-07 05:51:59 +00:00
TargetELFWriterInfo.h
TargetFrameLowering.h
TargetInstrInfo.h Simplify the computeOperandLatency API. 2012-08-23 00:39:43 +00:00
TargetIntrinsicInfo.h
TargetItinerary.td I'm introducing a new machine model to simultaneously allow simple 2012-07-07 04:00:00 +00:00
TargetJITInfo.h
TargetLibraryInfo.h Add a few functions to TargetLibraryInfo as part of PR13574. 2012-08-21 23:28:56 +00:00
TargetLowering.h Allow legalization of target-specific SDNodes, provided that the target itself provide a legalization hook for them. 2012-08-08 23:31:14 +00:00
TargetLoweringObjectFile.h
TargetMachine.h
TargetOpcodes.h
TargetOptions.h Add support for the --param ssp-buffer-size= driver option. 2012-08-21 16:15:24 +00:00
TargetRegisterInfo.h Add TargetRegisterInfo::hasRegUnit(). 2012-08-02 14:45:53 +00:00
TargetSchedule.td Added MispredictPenalty to SchedMachineModel. 2012-08-08 02:44:16 +00:00
TargetSelectionDAG.td Remove extra MayLoad/MayStore flags from atomic_load/store. 2012-08-28 03:11:32 +00:00
TargetSelectionDAGInfo.h
TargetSubtargetInfo.h