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llvm-mirror/lib/Target/AMDGPU
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Nicolai Haehnle 30a743add7 AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics 
Summary:
They correspond to BUFFER_LOAD/STORE_DWORD[_X2,X3,X4] and mostly behave like
llvm.amdgcn.buffer.load/store.format. They will be used by Mesa for SSBO and
atomic counters at least when robust buffer access behavior is desired.
(These instructions perform no format conversion and do buffer range checking
per component.)

As a side effect of sharing patterns with llvm.amdgcn.buffer.store.format,
it has become trivial to add support for the f32 and v2f32 variants of that
intrinsic, so the patch does so.

Also DAG-ify (and fix) some tests that I noticed intermittent failures in
while developing this patch.

Some tests were (temporarily) adjusted for the required mayLoad/hasSideEffects
changes to the BUFFER_STORE_DWORD* instructions. See also
http://reviews.llvm.org/D18291.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18292

llvm-svn: 266126
2016-04-12 21:18:10 +00:00
..
AsmParser [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3 2016-03-18 15:35:51 +00:00
Disassembler [AMDGPU] Disassembler: support for DPP 2016-03-31 14:15:04 +00:00
InstPrinter [AMDGPU] Assembler: Change dpp_ctrl syntax to match sp3 2016-03-18 15:35:51 +00:00
MCTargetDesc AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
TargetInfo
Utils Make helper functions static. NFC. 2016-04-07 10:10:09 +00:00
AMDGPU.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPU.td AMDGPU: More bits of frame index are known to be zero 2016-02-27 20:26:57 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
AMDGPUAsmPrinter.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUAsmPrinter.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUCallingConv.td AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
AMDGPUInstrInfo.td AMDGPU: Implement {BUFFER,FLAT}_ATOMIC_CMPSWAP{,_X2} 2016-04-01 18:27:37 +00:00
AMDGPUInstructions.td AMDGPU/SI: Implement atomic load/store for i32 and i64 2016-04-07 19:23:11 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUISelLowering.cpp AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUISelLowering.h AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
AMDGPUMachineFunction.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUMachineFunction.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUMCInstLower.cpp AMDGPU: Verify instructions in non-debug builds as well 2016-03-16 09:10:42 +00:00
AMDGPUMCInstLower.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
AMDGPUPromoteAlloca.cpp AMDGPU: Promote alloca should skip volatiles 2016-03-23 23:17:29 +00:00
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUSubtarget.h AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUTargetMachine.cpp AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
AMDGPUTargetMachine.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
AMDGPUTargetTransformInfo.h AMDGPU: Partially implement getArithmeticInstrCost for FP ops 2016-03-25 01:00:32 +00:00
AMDILCFGStructurizer.cpp Bug 20810: Use report_fatal_error instead of unreachable 2016-03-02 03:33:55 +00:00
AMDKernelCodeT.h [AMDGPU] fix amd_kernel_code_t bit field position as per spec (added missing reserved fields) 2016-02-24 10:54:25 +00:00
CaymanInstructions.td
CIInstructions.td AMDGPU: Implement i64 global atomics 2016-04-12 14:05:11 +00:00
CMakeLists.txt AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
EvergreenInstructions.td
LLVMBuild.txt [AMDGPU] Disassembler: Added basic disassembler for AMDGPU target 2016-02-18 03:42:32 +00:00
Processors.td AMDGPU/SI: Add Polaris support 2016-03-24 15:31:05 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600Defines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600InstrInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600Instructions.td AMDGPU: Rename intrinsic to better match instruction name 2016-02-13 01:03:00 +00:00
R600Intrinsics.td
R600ISelLowering.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
R600ISelLowering.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600MachineScheduler.cpp
R600MachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp AMDGPU: Simplify boolean conditional return statements 2016-03-02 23:00:21 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp AMDGPU/SI: Fix a mis-compilation of multi-level breaks 2016-04-12 16:10:38 +00:00
SIDefines.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIFixControlFlowLiveIntervals.cpp
SIFixSGPRCopies.cpp
SIFixSGPRLiveRanges.cpp AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SIFoldOperands.cpp
SIFrameLowering.cpp AMDGPU/SI: Don't try to move scratch wave offset when there are no free SGPRs 2016-03-03 03:45:09 +00:00
SIFrameLowering.h
SIInsertNopsPass.cpp AMDGPU: Insert two S_NOP instructions for every high level source statement. 2016-03-03 03:53:29 +00:00
SIInsertWaits.cpp AMDGPU/SI: Insert wait states required after v_readfirstlane on SI 2016-04-12 18:40:43 +00:00
SIInstrFormats.td [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields. 2016-04-01 13:13:12 +00:00
SIInstrInfo.cpp AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates 2016-04-07 14:47:07 +00:00
SIInstrInfo.h AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates 2016-04-07 14:47:07 +00:00
SIInstrInfo.td AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
SIInstructions.td AMDGPU: add llvm.amdgcn.buffer.load/store intrinsics 2016-04-12 21:18:10 +00:00
SIIntrinsics.td
SIISelLowering.cpp AMDGPU: Eliminate half of i64 or if one operand is zero_extend from i32 2016-04-12 18:24:38 +00:00
SIISelLowering.h AMDGPU: Add atomic_inc + atomic_dec intrinsics 2016-04-12 14:05:04 +00:00
SILoadStoreOptimizer.cpp Test commit access 2016-03-29 15:15:44 +00:00
SILowerControlFlow.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SIMachineFunctionInfo.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIMachineScheduler.cpp [TII] Allow getMemOpBaseRegImmOfs() to accept negative offsets. NFC. 2016-03-09 16:00:35 +00:00
SIMachineScheduler.h AMDGPU: R600 code splitting cleanup 2016-03-11 08:00:27 +00:00
SIRegisterInfo.cpp AMDGPU/SI: Add MachineBasicBlock parameter to SIInstrInfo::insertWaitStates 2016-04-07 14:47:07 +00:00
SIRegisterInfo.h AMDGPU: Cache information about register pressure sets 2016-03-23 01:53:22 +00:00
SIRegisterInfo.td AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions 2016-02-12 23:45:29 +00:00
SISchedule.td AMDGPU/SI: Improve MachineSchedModel definition 2016-03-30 16:35:13 +00:00
SIShrinkInstructions.cpp AMDGPU: Materialize sign bits with bfrev 2016-03-11 07:42:49 +00:00
SITypeRewriter.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
SIWholeQuadMode.cpp AMDGPU: Add a shader calling convention 2016-04-06 19:40:20 +00:00
VIInstrFormats.td [AMDGPU] Fix SMEM instructions encoding/operand namings 2016-03-10 13:06:08 +00:00
VIInstructions.td [AMDGPU] Assembler: change v_madmk operands to have same order as mad. 2016-03-11 09:27:25 +00:00