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29117fd386
by replacing DenseMap with IndexedMap for LLTs within MRI, as benchmarked by cross-compiling sqlite3 amalgamation for AArch64 on x86 machine. Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46809 llvm-svn: 333125
1195 lines
46 KiB
C++
1195 lines
46 KiB
C++
//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/PointerUnion.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/MC/LaneBitmask.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <iterator>
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#include <memory>
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#include <utility>
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#include <vector>
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namespace llvm {
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class PSetIterator;
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/// Convenient type to represent either a register class or a register bank.
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using RegClassOrRegBank =
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PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
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/// MachineRegisterInfo - Keep track of information for virtual and physical
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/// registers, including vreg register classes, use/def chains for registers,
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/// etc.
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class MachineRegisterInfo {
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public:
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class Delegate {
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virtual void anchor();
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public:
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virtual ~Delegate() = default;
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virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
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};
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private:
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MachineFunction *MF;
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Delegate *TheDelegate = nullptr;
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/// True if subregister liveness is tracked.
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const bool TracksSubRegLiveness;
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/// VRegInfo - Information we keep for each virtual register.
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///
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/// Each element in this list contains the register class of the vreg and the
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/// start of the use/def list for the register.
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IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
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VirtReg2IndexFunctor>
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VRegInfo;
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/// Map for recovering vreg name from vreg number.
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/// This map is used by the MIR Printer.
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IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name;
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/// StringSet that is used to unique vreg names.
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StringSet<> VRegNames;
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/// The flag is true upon \p UpdatedCSRs initialization
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/// and false otherwise.
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bool IsUpdatedCSRsInitialized;
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/// Contains the updated callee saved register list.
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/// As opposed to the static list defined in register info,
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/// all registers that were disabled are removed from the list.
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SmallVector<MCPhysReg, 16> UpdatedCSRs;
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/// RegAllocHints - This vector records register allocation hints for
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/// virtual registers. For each virtual register, it keeps a pair of hint
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/// type and hints vector making up the allocation hints. Only the first
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/// hint may be target specific, and in that case this is reflected by the
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/// first member of the pair being non-zero. If the hinted register is
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/// virtual, it means the allocator should prefer the physical register
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/// allocated to it if any.
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IndexedMap<std::pair<unsigned, SmallVector<unsigned, 4>>,
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VirtReg2IndexFunctor> RegAllocHints;
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/// PhysRegUseDefLists - This is an array of the head of the use/def list for
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/// physical registers.
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std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// list for the specified virtual or physical register.
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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}
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MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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}
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/// Get the next element in the use-def chain.
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static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
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assert(MO && MO->isReg() && "This is not a register operand!");
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return MO->Contents.Reg.Next;
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}
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/// UsedPhysRegMask - Additional used physregs including aliases.
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/// This bit vector represents all the registers clobbered by function calls.
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BitVector UsedPhysRegMask;
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/// ReservedRegs - This is a bit vector of reserved registers. The target
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/// may change its mind about which registers should be reserved. This
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/// vector is the frozen set of reserved registers when register allocation
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/// started.
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BitVector ReservedRegs;
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using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;
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/// Map generic virtual registers to their low-level type.
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VRegToTypeMap VRegToType;
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/// Keep track of the physical registers that are live in to the function.
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/// Live in values are typically arguments in registers. LiveIn values are
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/// allowed to have virtual registers associated with them, stored in the
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/// second element.
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std::vector<std::pair<unsigned, unsigned>> LiveIns;
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public:
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explicit MachineRegisterInfo(MachineFunction *MF);
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MachineRegisterInfo(const MachineRegisterInfo &) = delete;
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MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
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const TargetRegisterInfo *getTargetRegisterInfo() const {
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return MF->getSubtarget().getRegisterInfo();
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}
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void resetDelegate(Delegate *delegate) {
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// Ensure another delegate does not take over unless the current
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// delegate first unattaches itself. If we ever need to multicast
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// notifications, we will need to change to using a list.
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assert(TheDelegate == delegate &&
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"Only the current delegate can perform reset!");
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TheDelegate = nullptr;
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}
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void setDelegate(Delegate *delegate) {
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assert(delegate && !TheDelegate &&
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"Attempted to set delegate to null, or to change it without "
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"first resetting it!");
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TheDelegate = delegate;
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}
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//===--------------------------------------------------------------------===//
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// Function State
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//===--------------------------------------------------------------------===//
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// isSSA - Returns true when the machine function is in SSA form. Early
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// passes require the machine function to be in SSA form where every virtual
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// register has a single defining instruction.
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//
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// The TwoAddressInstructionPass and PHIElimination passes take the machine
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// function out of SSA form when they introduce multiple defs per virtual
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// register.
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bool isSSA() const {
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return MF->getProperties().hasProperty(
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MachineFunctionProperties::Property::IsSSA);
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}
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// leaveSSA - Indicates that the machine function is no longer in SSA form.
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void leaveSSA() {
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MF->getProperties().reset(MachineFunctionProperties::Property::IsSSA);
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}
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/// tracksLiveness - Returns true when tracking register liveness accurately.
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/// (see MachineFUnctionProperties::Property description for details)
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bool tracksLiveness() const {
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return MF->getProperties().hasProperty(
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MachineFunctionProperties::Property::TracksLiveness);
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}
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/// invalidateLiveness - Indicates that register liveness is no longer being
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/// tracked accurately.
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///
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/// This should be called by late passes that invalidate the liveness
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/// information.
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void invalidateLiveness() {
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MF->getProperties().reset(
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MachineFunctionProperties::Property::TracksLiveness);
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}
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/// Returns true if liveness for register class @p RC should be tracked at
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/// the subregister level.
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bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
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return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
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}
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bool shouldTrackSubRegLiveness(unsigned VReg) const {
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assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
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return shouldTrackSubRegLiveness(*getRegClass(VReg));
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}
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bool subRegLivenessEnabled() const {
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return TracksSubRegLiveness;
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}
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//===--------------------------------------------------------------------===//
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// Register Info
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//===--------------------------------------------------------------------===//
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/// Returns true if the updated CSR list was initialized and false otherwise.
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bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; }
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/// Disables the register from the list of CSRs.
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/// I.e. the register will not appear as part of the CSR mask.
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/// \see UpdatedCalleeSavedRegs.
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void disableCalleeSavedRegister(unsigned Reg);
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/// Returns list of callee saved registers.
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/// The function returns the updated CSR list (after taking into account
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/// registers that are disabled from the CSR list).
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const MCPhysReg *getCalleeSavedRegs() const;
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/// Sets the updated Callee Saved Registers list.
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/// Notice that it will override ant previously disabled/saved CSRs.
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void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs);
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// Strictly for use by MachineInstr.cpp.
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void addRegOperandToUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void removeRegOperandFromUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
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/// Verify the sanity of the use list for Reg.
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void verifyUseList(unsigned Reg) const;
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/// Verify the use list of all registers.
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void verifyUseLists() const;
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/// reg_begin/reg_end - Provide iteration support to walk over all definitions
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/// and uses of a register within the MachineFunction that corresponds to this
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/// MachineRegisterInfo object.
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template<bool Uses, bool Defs, bool SkipDebug,
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bool ByOperand, bool ByInstr, bool ByBundle>
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class defusechain_iterator;
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template<bool Uses, bool Defs, bool SkipDebug,
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bool ByOperand, bool ByInstr, bool ByBundle>
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class defusechain_instr_iterator;
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// Make it a friend so it can access getNextOperandForReg().
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template<bool, bool, bool, bool, bool, bool>
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friend class defusechain_iterator;
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template<bool, bool, bool, bool, bool, bool>
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friend class defusechain_instr_iterator;
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/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
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/// register.
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using reg_iterator =
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defusechain_iterator<true, true, false, true, false, false>;
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reg_iterator reg_begin(unsigned RegNo) const {
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return reg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_iterator reg_end() { return reg_iterator(nullptr); }
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inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
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return make_range(reg_begin(Reg), reg_end());
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}
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/// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
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/// of the specified register, stepping by MachineInstr.
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using reg_instr_iterator =
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defusechain_instr_iterator<true, true, false, false, true, false>;
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reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
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return reg_instr_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_instr_iterator reg_instr_end() {
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return reg_instr_iterator(nullptr);
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}
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inline iterator_range<reg_instr_iterator>
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reg_instructions(unsigned Reg) const {
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return make_range(reg_instr_begin(Reg), reg_instr_end());
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}
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/// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
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/// of the specified register, stepping by bundle.
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using reg_bundle_iterator =
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defusechain_instr_iterator<true, true, false, false, false, true>;
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reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
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return reg_bundle_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_bundle_iterator reg_bundle_end() {
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return reg_bundle_iterator(nullptr);
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}
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inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
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return make_range(reg_bundle_begin(Reg), reg_bundle_end());
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}
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/// reg_empty - Return true if there are no instructions using or defining the
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/// specified register (it may be live-in).
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bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
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/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
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/// of the specified register, skipping those marked as Debug.
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using reg_nodbg_iterator =
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defusechain_iterator<true, true, true, true, false, false>;
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reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
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return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_nodbg_iterator reg_nodbg_end() {
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return reg_nodbg_iterator(nullptr);
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}
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inline iterator_range<reg_nodbg_iterator>
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reg_nodbg_operands(unsigned Reg) const {
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return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
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}
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/// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
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/// all defs and uses of the specified register, stepping by MachineInstr,
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/// skipping those marked as Debug.
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using reg_instr_nodbg_iterator =
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defusechain_instr_iterator<true, true, true, false, true, false>;
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reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
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return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
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return reg_instr_nodbg_iterator(nullptr);
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}
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inline iterator_range<reg_instr_nodbg_iterator>
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reg_nodbg_instructions(unsigned Reg) const {
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return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
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}
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/// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
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/// all defs and uses of the specified register, stepping by bundle,
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/// skipping those marked as Debug.
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using reg_bundle_nodbg_iterator =
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defusechain_instr_iterator<true, true, true, false, false, true>;
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reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
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return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
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return reg_bundle_nodbg_iterator(nullptr);
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}
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inline iterator_range<reg_bundle_nodbg_iterator>
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reg_nodbg_bundles(unsigned Reg) const {
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return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
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}
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/// reg_nodbg_empty - Return true if the only instructions using or defining
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/// Reg are Debug instructions.
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bool reg_nodbg_empty(unsigned RegNo) const {
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return reg_nodbg_begin(RegNo) == reg_nodbg_end();
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}
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/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
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using def_iterator =
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defusechain_iterator<false, true, false, true, false, false>;
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def_iterator def_begin(unsigned RegNo) const {
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return def_iterator(getRegUseDefListHead(RegNo));
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}
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static def_iterator def_end() { return def_iterator(nullptr); }
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inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
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return make_range(def_begin(Reg), def_end());
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}
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/// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
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/// specified register, stepping by MachineInst.
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using def_instr_iterator =
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defusechain_instr_iterator<false, true, false, false, true, false>;
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def_instr_iterator def_instr_begin(unsigned RegNo) const {
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return def_instr_iterator(getRegUseDefListHead(RegNo));
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}
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static def_instr_iterator def_instr_end() {
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return def_instr_iterator(nullptr);
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}
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inline iterator_range<def_instr_iterator>
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def_instructions(unsigned Reg) const {
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return make_range(def_instr_begin(Reg), def_instr_end());
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}
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/// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
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/// specified register, stepping by bundle.
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using def_bundle_iterator =
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defusechain_instr_iterator<false, true, false, false, false, true>;
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def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
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return def_bundle_iterator(getRegUseDefListHead(RegNo));
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}
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static def_bundle_iterator def_bundle_end() {
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return def_bundle_iterator(nullptr);
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}
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inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
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return make_range(def_bundle_begin(Reg), def_bundle_end());
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}
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/// def_empty - Return true if there are no instructions defining the
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/// specified register (it may be live-in).
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bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
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StringRef getVRegName(unsigned Reg) const {
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return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
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}
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void insertVRegByName(StringRef Name, unsigned Reg) {
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assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
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"Named VRegs Must be Unique.");
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if (!Name.empty()) {
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VRegNames.insert(Name);
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VReg2Name.grow(Reg);
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VReg2Name[Reg] = Name.str();
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}
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}
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/// Return true if there is exactly one operand defining the specified
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/// register.
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bool hasOneDef(unsigned RegNo) const {
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def_iterator DI = def_begin(RegNo);
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if (DI == def_end())
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return false;
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return ++DI == def_end();
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}
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/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
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using use_iterator =
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defusechain_iterator<true, false, false, true, false, false>;
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use_iterator use_begin(unsigned RegNo) const {
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return use_iterator(getRegUseDefListHead(RegNo));
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}
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static use_iterator use_end() { return use_iterator(nullptr); }
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inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
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return make_range(use_begin(Reg), use_end());
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}
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/// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
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/// specified register, stepping by MachineInstr.
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using use_instr_iterator =
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defusechain_instr_iterator<true, false, false, false, true, false>;
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use_instr_iterator use_instr_begin(unsigned RegNo) const {
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return use_instr_iterator(getRegUseDefListHead(RegNo));
|
|
}
|
|
static use_instr_iterator use_instr_end() {
|
|
return use_instr_iterator(nullptr);
|
|
}
|
|
|
|
inline iterator_range<use_instr_iterator>
|
|
use_instructions(unsigned Reg) const {
|
|
return make_range(use_instr_begin(Reg), use_instr_end());
|
|
}
|
|
|
|
/// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
|
|
/// specified register, stepping by bundle.
|
|
using use_bundle_iterator =
|
|
defusechain_instr_iterator<true, false, false, false, false, true>;
|
|
use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
|
|
return use_bundle_iterator(getRegUseDefListHead(RegNo));
|
|
}
|
|
static use_bundle_iterator use_bundle_end() {
|
|
return use_bundle_iterator(nullptr);
|
|
}
|
|
|
|
inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
|
|
return make_range(use_bundle_begin(Reg), use_bundle_end());
|
|
}
|
|
|
|
/// use_empty - Return true if there are no instructions using the specified
|
|
/// register.
|
|
bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
|
|
|
|
/// hasOneUse - Return true if there is exactly one instruction using the
|
|
/// specified register.
|
|
bool hasOneUse(unsigned RegNo) const {
|
|
use_iterator UI = use_begin(RegNo);
|
|
if (UI == use_end())
|
|
return false;
|
|
return ++UI == use_end();
|
|
}
|
|
|
|
/// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
|
|
/// specified register, skipping those marked as Debug.
|
|
using use_nodbg_iterator =
|
|
defusechain_iterator<true, false, true, true, false, false>;
|
|
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
|
|
return use_nodbg_iterator(getRegUseDefListHead(RegNo));
|
|
}
|
|
static use_nodbg_iterator use_nodbg_end() {
|
|
return use_nodbg_iterator(nullptr);
|
|
}
|
|
|
|
inline iterator_range<use_nodbg_iterator>
|
|
use_nodbg_operands(unsigned Reg) const {
|
|
return make_range(use_nodbg_begin(Reg), use_nodbg_end());
|
|
}
|
|
|
|
/// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
|
|
/// all uses of the specified register, stepping by MachineInstr, skipping
|
|
/// those marked as Debug.
|
|
using use_instr_nodbg_iterator =
|
|
defusechain_instr_iterator<true, false, true, false, true, false>;
|
|
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
|
|
return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
|
|
}
|
|
static use_instr_nodbg_iterator use_instr_nodbg_end() {
|
|
return use_instr_nodbg_iterator(nullptr);
|
|
}
|
|
|
|
inline iterator_range<use_instr_nodbg_iterator>
|
|
use_nodbg_instructions(unsigned Reg) const {
|
|
return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
|
|
}
|
|
|
|
/// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
|
|
/// all uses of the specified register, stepping by bundle, skipping
|
|
/// those marked as Debug.
|
|
using use_bundle_nodbg_iterator =
|
|
defusechain_instr_iterator<true, false, true, false, false, true>;
|
|
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
|
|
return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
|
|
}
|
|
static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
|
|
return use_bundle_nodbg_iterator(nullptr);
|
|
}
|
|
|
|
inline iterator_range<use_bundle_nodbg_iterator>
|
|
use_nodbg_bundles(unsigned Reg) const {
|
|
return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
|
|
}
|
|
|
|
/// use_nodbg_empty - Return true if there are no non-Debug instructions
|
|
/// using the specified register.
|
|
bool use_nodbg_empty(unsigned RegNo) const {
|
|
return use_nodbg_begin(RegNo) == use_nodbg_end();
|
|
}
|
|
|
|
/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
|
|
/// instruction using the specified register.
|
|
bool hasOneNonDBGUse(unsigned RegNo) const;
|
|
|
|
/// replaceRegWith - Replace all instances of FromReg with ToReg in the
|
|
/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
|
|
/// except that it also changes any definitions of the register as well.
|
|
///
|
|
/// Note that it is usually necessary to first constrain ToReg's register
|
|
/// class and register bank to match the FromReg constraints using one of the
|
|
/// methods:
|
|
///
|
|
/// constrainRegClass(ToReg, getRegClass(FromReg))
|
|
/// constrainRegAttrs(ToReg, FromReg)
|
|
/// RegisterBankInfo::constrainGenericRegister(ToReg,
|
|
/// *MRI.getRegClass(FromReg), MRI)
|
|
///
|
|
/// These functions will return a falsy result if the virtual registers have
|
|
/// incompatible constraints.
|
|
///
|
|
/// Note that if ToReg is a physical register the function will replace and
|
|
/// apply sub registers to ToReg in order to obtain a final/proper physical
|
|
/// register.
|
|
void replaceRegWith(unsigned FromReg, unsigned ToReg);
|
|
|
|
/// getVRegDef - Return the machine instr that defines the specified virtual
|
|
/// register or null if none is found. This assumes that the code is in SSA
|
|
/// form, so there should only be one definition.
|
|
MachineInstr *getVRegDef(unsigned Reg) const;
|
|
|
|
/// getUniqueVRegDef - Return the unique machine instr that defines the
|
|
/// specified virtual register or null if none is found. If there are
|
|
/// multiple definitions or no definition, return null.
|
|
MachineInstr *getUniqueVRegDef(unsigned Reg) const;
|
|
|
|
/// clearKillFlags - Iterate over all the uses of the given register and
|
|
/// clear the kill flag from the MachineOperand. This function is used by
|
|
/// optimization passes which extend register lifetimes and need only
|
|
/// preserve conservative kill flag information.
|
|
void clearKillFlags(unsigned Reg) const;
|
|
|
|
void dumpUses(unsigned RegNo) const;
|
|
|
|
/// Returns true if PhysReg is unallocatable and constant throughout the
|
|
/// function. Writing to a constant register has no effect.
|
|
bool isConstantPhysReg(unsigned PhysReg) const;
|
|
|
|
/// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
|
|
/// returns true. This is a utility member function.
|
|
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
|
|
|
|
/// Get an iterator over the pressure sets affected by the given physical or
|
|
/// virtual register. If RegUnit is physical, it must be a register unit (from
|
|
/// MCRegUnitIterator).
|
|
PSetIterator getPressureSets(unsigned RegUnit) const;
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Virtual Register Info
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// Return the register class of the specified virtual register.
|
|
/// This shouldn't be used directly unless \p Reg has a register class.
|
|
/// \see getRegClassOrNull when this might happen.
|
|
const TargetRegisterClass *getRegClass(unsigned Reg) const {
|
|
assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
|
|
"Register class not set, wrong accessor");
|
|
return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
|
|
}
|
|
|
|
/// Return the register class of \p Reg, or null if Reg has not been assigned
|
|
/// a register class yet.
|
|
///
|
|
/// \note A null register class can only happen when these two
|
|
/// conditions are met:
|
|
/// 1. Generic virtual registers are created.
|
|
/// 2. The machine function has not completely been through the
|
|
/// instruction selection process.
|
|
/// None of this condition is possible without GlobalISel for now.
|
|
/// In other words, if GlobalISel is not used or if the query happens after
|
|
/// the select pass, using getRegClass is safe.
|
|
const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
|
|
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
|
|
return Val.dyn_cast<const TargetRegisterClass *>();
|
|
}
|
|
|
|
/// Return the register bank of \p Reg, or null if Reg has not been assigned
|
|
/// a register bank or has been assigned a register class.
|
|
/// \note It is possible to get the register bank from the register class via
|
|
/// RegisterBankInfo::getRegBankFromRegClass.
|
|
const RegisterBank *getRegBankOrNull(unsigned Reg) const {
|
|
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
|
|
return Val.dyn_cast<const RegisterBank *>();
|
|
}
|
|
|
|
/// Return the register bank or register class of \p Reg.
|
|
/// \note Before the register bank gets assigned (i.e., before the
|
|
/// RegBankSelect pass) \p Reg may not have either.
|
|
const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
|
|
return VRegInfo[Reg].first;
|
|
}
|
|
|
|
/// setRegClass - Set the register class of the specified virtual register.
|
|
void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
|
|
|
|
/// Set the register bank to \p RegBank for \p Reg.
|
|
void setRegBank(unsigned Reg, const RegisterBank &RegBank);
|
|
|
|
void setRegClassOrRegBank(unsigned Reg,
|
|
const RegClassOrRegBank &RCOrRB){
|
|
VRegInfo[Reg].first = RCOrRB;
|
|
}
|
|
|
|
/// constrainRegClass - Constrain the register class of the specified virtual
|
|
/// register to be a common subclass of RC and the current register class,
|
|
/// but only if the new class has at least MinNumRegs registers. Return the
|
|
/// new register class, or NULL if no such class exists.
|
|
/// This should only be used when the constraint is known to be trivial, like
|
|
/// GR32 -> GR32_NOSP. Beware of increasing register pressure.
|
|
///
|
|
/// \note Assumes that the register has a register class assigned.
|
|
/// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
|
|
/// InstructionSelect pass and constrainRegAttrs in every other pass,
|
|
/// including non-select passes of GlobalISel, instead.
|
|
const TargetRegisterClass *constrainRegClass(unsigned Reg,
|
|
const TargetRegisterClass *RC,
|
|
unsigned MinNumRegs = 0);
|
|
|
|
/// Constrain the register class or the register bank of the virtual register
|
|
/// \p Reg to be a common subclass and a common bank of both registers
|
|
/// provided respectively. Do nothing if any of the attributes (classes,
|
|
/// banks, or low-level types) of the registers are deemed incompatible, or if
|
|
/// the resulting register will have a class smaller than before and of size
|
|
/// less than \p MinNumRegs. Return true if such register attributes exist,
|
|
/// false otherwise.
|
|
///
|
|
/// \note Assumes that each register has either a low-level type or a class
|
|
/// assigned, but not both. Use this method instead of constrainRegClass and
|
|
/// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
|
|
/// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
|
|
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
|
|
unsigned MinNumRegs = 0);
|
|
|
|
/// recomputeRegClass - Try to find a legal super-class of Reg's register
|
|
/// class that still satisfies the constraints from the instructions using
|
|
/// Reg. Returns true if Reg was upgraded.
|
|
///
|
|
/// This method can be used after constraints have been removed from a
|
|
/// virtual register, for example after removing instructions or splitting
|
|
/// the live range.
|
|
bool recomputeRegClass(unsigned Reg);
|
|
|
|
/// createVirtualRegister - Create and return a new virtual register in the
|
|
/// function with the specified register class.
|
|
unsigned createVirtualRegister(const TargetRegisterClass *RegClass,
|
|
StringRef Name = "");
|
|
|
|
/// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
|
|
/// (target independent) virtual register.
|
|
LLT getType(unsigned Reg) const {
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
|
|
return VRegToType[Reg];
|
|
return LLT{};
|
|
}
|
|
|
|
/// Set the low-level type of \p VReg to \p Ty.
|
|
void setType(unsigned VReg, LLT Ty);
|
|
|
|
/// Create and return a new generic virtual register with low-level
|
|
/// type \p Ty.
|
|
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name = "");
|
|
|
|
/// Remove all types associated to virtual registers (after instruction
|
|
/// selection and constraining of all generic virtual registers).
|
|
void clearVirtRegTypes();
|
|
|
|
/// Creates a new virtual register that has no register class, register bank
|
|
/// or size assigned yet. This is only allowed to be used
|
|
/// temporarily while constructing machine instructions. Most operations are
|
|
/// undefined on an incomplete register until one of setRegClass(),
|
|
/// setRegBank() or setSize() has been called on it.
|
|
unsigned createIncompleteVirtualRegister(StringRef Name = "");
|
|
|
|
/// getNumVirtRegs - Return the number of virtual registers created.
|
|
unsigned getNumVirtRegs() const { return VRegInfo.size(); }
|
|
|
|
/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
|
|
void clearVirtRegs();
|
|
|
|
/// setRegAllocationHint - Specify a register allocation hint for the
|
|
/// specified virtual register. This is typically used by target, and in case
|
|
/// of an earlier hint it will be overwritten.
|
|
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
|
|
assert(TargetRegisterInfo::isVirtualRegister(VReg));
|
|
RegAllocHints[VReg].first = Type;
|
|
RegAllocHints[VReg].second.clear();
|
|
RegAllocHints[VReg].second.push_back(PrefReg);
|
|
}
|
|
|
|
/// addRegAllocationHint - Add a register allocation hint to the hints
|
|
/// vector for VReg.
|
|
void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
|
|
assert(TargetRegisterInfo::isVirtualRegister(VReg));
|
|
RegAllocHints[VReg].second.push_back(PrefReg);
|
|
}
|
|
|
|
/// Specify the preferred (target independent) register allocation hint for
|
|
/// the specified virtual register.
|
|
void setSimpleHint(unsigned VReg, unsigned PrefReg) {
|
|
setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
|
|
}
|
|
|
|
void clearSimpleHint(unsigned VReg) {
|
|
assert (RegAllocHints[VReg].first == 0 &&
|
|
"Expected to clear a non-target hint!");
|
|
RegAllocHints[VReg].second.clear();
|
|
}
|
|
|
|
/// getRegAllocationHint - Return the register allocation hint for the
|
|
/// specified virtual register. If there are many hints, this returns the
|
|
/// one with the greatest weight.
|
|
std::pair<unsigned, unsigned>
|
|
getRegAllocationHint(unsigned VReg) const {
|
|
assert(TargetRegisterInfo::isVirtualRegister(VReg));
|
|
unsigned BestHint = (RegAllocHints[VReg].second.size() ?
|
|
RegAllocHints[VReg].second[0] : 0);
|
|
return std::pair<unsigned, unsigned>(RegAllocHints[VReg].first, BestHint);
|
|
}
|
|
|
|
/// getSimpleHint - same as getRegAllocationHint except it will only return
|
|
/// a target independent hint.
|
|
unsigned getSimpleHint(unsigned VReg) const {
|
|
assert(TargetRegisterInfo::isVirtualRegister(VReg));
|
|
std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
|
|
return Hint.first ? 0 : Hint.second;
|
|
}
|
|
|
|
/// getRegAllocationHints - Return a reference to the vector of all
|
|
/// register allocation hints for VReg.
|
|
const std::pair<unsigned, SmallVector<unsigned, 4>>
|
|
&getRegAllocationHints(unsigned VReg) const {
|
|
assert(TargetRegisterInfo::isVirtualRegister(VReg));
|
|
return RegAllocHints[VReg];
|
|
}
|
|
|
|
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
|
|
/// specified register as undefined which causes the DBG_VALUE to be
|
|
/// deleted during LiveDebugVariables analysis.
|
|
void markUsesInDebugValueAsUndef(unsigned Reg) const;
|
|
|
|
/// Return true if the specified register is modified in this function.
|
|
/// This checks that no defining machine operands exist for the register or
|
|
/// any of its aliases. Definitions found on functions marked noreturn are
|
|
/// ignored, to consider them pass 'true' for optional parameter
|
|
/// SkipNoReturnDef. The register is also considered modified when it is set
|
|
/// in the UsedPhysRegMask.
|
|
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
|
|
|
|
/// Return true if the specified register is modified or read in this
|
|
/// function. This checks that no machine operands exist for the register or
|
|
/// any of its aliases. The register is also considered used when it is set
|
|
/// in the UsedPhysRegMask.
|
|
bool isPhysRegUsed(unsigned PhysReg) const;
|
|
|
|
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
|
|
/// This corresponds to the bit mask attached to register mask operands.
|
|
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
|
|
UsedPhysRegMask.setBitsNotInMask(RegMask);
|
|
}
|
|
|
|
const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Reserved Register Info
|
|
//===--------------------------------------------------------------------===//
|
|
//
|
|
// The set of reserved registers must be invariant during register
|
|
// allocation. For example, the target cannot suddenly decide it needs a
|
|
// frame pointer when the register allocator has already used the frame
|
|
// pointer register for something else.
|
|
//
|
|
// These methods can be used by target hooks like hasFP() to avoid changing
|
|
// the reserved register set during register allocation.
|
|
|
|
/// freezeReservedRegs - Called by the register allocator to freeze the set
|
|
/// of reserved registers before allocation begins.
|
|
void freezeReservedRegs(const MachineFunction&);
|
|
|
|
/// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
|
|
/// to ensure the set of reserved registers stays constant.
|
|
bool reservedRegsFrozen() const {
|
|
return !ReservedRegs.empty();
|
|
}
|
|
|
|
/// canReserveReg - Returns true if PhysReg can be used as a reserved
|
|
/// register. Any register can be reserved before freezeReservedRegs() is
|
|
/// called.
|
|
bool canReserveReg(unsigned PhysReg) const {
|
|
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
|
|
}
|
|
|
|
/// getReservedRegs - Returns a reference to the frozen set of reserved
|
|
/// registers. This method should always be preferred to calling
|
|
/// TRI::getReservedRegs() when possible.
|
|
const BitVector &getReservedRegs() const {
|
|
assert(reservedRegsFrozen() &&
|
|
"Reserved registers haven't been frozen yet. "
|
|
"Use TRI::getReservedRegs().");
|
|
return ReservedRegs;
|
|
}
|
|
|
|
/// isReserved - Returns true when PhysReg is a reserved register.
|
|
///
|
|
/// Reserved registers may belong to an allocatable register class, but the
|
|
/// target has explicitly requested that they are not used.
|
|
bool isReserved(unsigned PhysReg) const {
|
|
return getReservedRegs().test(PhysReg);
|
|
}
|
|
|
|
/// Returns true when the given register unit is considered reserved.
|
|
///
|
|
/// Register units are considered reserved when for at least one of their
|
|
/// root registers, the root register and all super registers are reserved.
|
|
/// This currently iterates the register hierarchy and may be slower than
|
|
/// expected.
|
|
bool isReservedRegUnit(unsigned Unit) const;
|
|
|
|
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
|
|
/// register class and it hasn't been reserved.
|
|
///
|
|
/// Allocatable registers may show up in the allocation order of some virtual
|
|
/// register, so a register allocator needs to track its liveness and
|
|
/// availability.
|
|
bool isAllocatable(unsigned PhysReg) const {
|
|
return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
|
|
!isReserved(PhysReg);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// LiveIn Management
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// addLiveIn - Add the specified register as a live-in. Note that it
|
|
/// is an error to add the same register to the same set more than once.
|
|
void addLiveIn(unsigned Reg, unsigned vreg = 0) {
|
|
LiveIns.push_back(std::make_pair(Reg, vreg));
|
|
}
|
|
|
|
// Iteration support for the live-ins set. It's kept in sorted order
|
|
// by register number.
|
|
using livein_iterator =
|
|
std::vector<std::pair<unsigned,unsigned>>::const_iterator;
|
|
livein_iterator livein_begin() const { return LiveIns.begin(); }
|
|
livein_iterator livein_end() const { return LiveIns.end(); }
|
|
bool livein_empty() const { return LiveIns.empty(); }
|
|
|
|
ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
|
|
return LiveIns;
|
|
}
|
|
|
|
bool isLiveIn(unsigned Reg) const;
|
|
|
|
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
|
|
/// corresponding live-in physical register.
|
|
unsigned getLiveInPhysReg(unsigned VReg) const;
|
|
|
|
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
|
|
/// corresponding live-in physical register.
|
|
unsigned getLiveInVirtReg(unsigned PReg) const;
|
|
|
|
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
|
|
/// into the given entry block.
|
|
void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
|
|
const TargetRegisterInfo &TRI,
|
|
const TargetInstrInfo &TII);
|
|
|
|
/// Returns a mask covering all bits that can appear in lane masks of
|
|
/// subregisters of the virtual register @p Reg.
|
|
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
|
|
|
|
/// defusechain_iterator - This class provides iterator support for machine
|
|
/// operands in the function that use or define a specific register. If
|
|
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
|
|
/// returns defs. If neither are true then you are silly and it always
|
|
/// returns end(). If SkipDebug is true it skips uses marked Debug
|
|
/// when incrementing.
|
|
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
|
|
bool ByOperand, bool ByInstr, bool ByBundle>
|
|
class defusechain_iterator
|
|
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
|
|
friend class MachineRegisterInfo;
|
|
|
|
MachineOperand *Op = nullptr;
|
|
|
|
explicit defusechain_iterator(MachineOperand *op) : Op(op) {
|
|
// If the first node isn't one we're interested in, advance to one that
|
|
// we are interested in.
|
|
if (op) {
|
|
if ((!ReturnUses && op->isUse()) ||
|
|
(!ReturnDefs && op->isDef()) ||
|
|
(SkipDebug && op->isDebug()))
|
|
advance();
|
|
}
|
|
}
|
|
|
|
void advance() {
|
|
assert(Op && "Cannot increment end iterator!");
|
|
Op = getNextOperandForReg(Op);
|
|
|
|
// All defs come before the uses, so stop def_iterator early.
|
|
if (!ReturnUses) {
|
|
if (Op) {
|
|
if (Op->isUse())
|
|
Op = nullptr;
|
|
else
|
|
assert(!Op->isDebug() && "Can't have debug defs");
|
|
}
|
|
} else {
|
|
// If this is an operand we don't care about, skip it.
|
|
while (Op && ((!ReturnDefs && Op->isDef()) ||
|
|
(SkipDebug && Op->isDebug())))
|
|
Op = getNextOperandForReg(Op);
|
|
}
|
|
}
|
|
|
|
public:
|
|
using reference = std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::reference;
|
|
using pointer = std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::pointer;
|
|
|
|
defusechain_iterator() = default;
|
|
|
|
bool operator==(const defusechain_iterator &x) const {
|
|
return Op == x.Op;
|
|
}
|
|
bool operator!=(const defusechain_iterator &x) const {
|
|
return !operator==(x);
|
|
}
|
|
|
|
/// atEnd - return true if this iterator is equal to reg_end() on the value.
|
|
bool atEnd() const { return Op == nullptr; }
|
|
|
|
// Iterator traversal: forward iteration only
|
|
defusechain_iterator &operator++() { // Preincrement
|
|
assert(Op && "Cannot increment end iterator!");
|
|
if (ByOperand)
|
|
advance();
|
|
else if (ByInstr) {
|
|
MachineInstr *P = Op->getParent();
|
|
do {
|
|
advance();
|
|
} while (Op && Op->getParent() == P);
|
|
} else if (ByBundle) {
|
|
MachineBasicBlock::instr_iterator P =
|
|
getBundleStart(Op->getParent()->getIterator());
|
|
do {
|
|
advance();
|
|
} while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
|
|
}
|
|
|
|
return *this;
|
|
}
|
|
defusechain_iterator operator++(int) { // Postincrement
|
|
defusechain_iterator tmp = *this; ++*this; return tmp;
|
|
}
|
|
|
|
/// getOperandNo - Return the operand # of this MachineOperand in its
|
|
/// MachineInstr.
|
|
unsigned getOperandNo() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return Op - &Op->getParent()->getOperand(0);
|
|
}
|
|
|
|
// Retrieve a reference to the current operand.
|
|
MachineOperand &operator*() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return *Op;
|
|
}
|
|
|
|
MachineOperand *operator->() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return Op;
|
|
}
|
|
};
|
|
|
|
/// defusechain_iterator - This class provides iterator support for machine
|
|
/// operands in the function that use or define a specific register. If
|
|
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
|
|
/// returns defs. If neither are true then you are silly and it always
|
|
/// returns end(). If SkipDebug is true it skips uses marked Debug
|
|
/// when incrementing.
|
|
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
|
|
bool ByOperand, bool ByInstr, bool ByBundle>
|
|
class defusechain_instr_iterator
|
|
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
|
|
friend class MachineRegisterInfo;
|
|
|
|
MachineOperand *Op = nullptr;
|
|
|
|
explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
|
|
// If the first node isn't one we're interested in, advance to one that
|
|
// we are interested in.
|
|
if (op) {
|
|
if ((!ReturnUses && op->isUse()) ||
|
|
(!ReturnDefs && op->isDef()) ||
|
|
(SkipDebug && op->isDebug()))
|
|
advance();
|
|
}
|
|
}
|
|
|
|
void advance() {
|
|
assert(Op && "Cannot increment end iterator!");
|
|
Op = getNextOperandForReg(Op);
|
|
|
|
// All defs come before the uses, so stop def_iterator early.
|
|
if (!ReturnUses) {
|
|
if (Op) {
|
|
if (Op->isUse())
|
|
Op = nullptr;
|
|
else
|
|
assert(!Op->isDebug() && "Can't have debug defs");
|
|
}
|
|
} else {
|
|
// If this is an operand we don't care about, skip it.
|
|
while (Op && ((!ReturnDefs && Op->isDef()) ||
|
|
(SkipDebug && Op->isDebug())))
|
|
Op = getNextOperandForReg(Op);
|
|
}
|
|
}
|
|
|
|
public:
|
|
using reference = std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::reference;
|
|
using pointer = std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::pointer;
|
|
|
|
defusechain_instr_iterator() = default;
|
|
|
|
bool operator==(const defusechain_instr_iterator &x) const {
|
|
return Op == x.Op;
|
|
}
|
|
bool operator!=(const defusechain_instr_iterator &x) const {
|
|
return !operator==(x);
|
|
}
|
|
|
|
/// atEnd - return true if this iterator is equal to reg_end() on the value.
|
|
bool atEnd() const { return Op == nullptr; }
|
|
|
|
// Iterator traversal: forward iteration only
|
|
defusechain_instr_iterator &operator++() { // Preincrement
|
|
assert(Op && "Cannot increment end iterator!");
|
|
if (ByOperand)
|
|
advance();
|
|
else if (ByInstr) {
|
|
MachineInstr *P = Op->getParent();
|
|
do {
|
|
advance();
|
|
} while (Op && Op->getParent() == P);
|
|
} else if (ByBundle) {
|
|
MachineBasicBlock::instr_iterator P =
|
|
getBundleStart(Op->getParent()->getIterator());
|
|
do {
|
|
advance();
|
|
} while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
|
|
}
|
|
|
|
return *this;
|
|
}
|
|
defusechain_instr_iterator operator++(int) { // Postincrement
|
|
defusechain_instr_iterator tmp = *this; ++*this; return tmp;
|
|
}
|
|
|
|
// Retrieve a reference to the current operand.
|
|
MachineInstr &operator*() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
if (ByBundle)
|
|
return *getBundleStart(Op->getParent()->getIterator());
|
|
return *Op->getParent();
|
|
}
|
|
|
|
MachineInstr *operator->() const { return &operator*(); }
|
|
};
|
|
};
|
|
|
|
/// Iterate over the pressure sets affected by the given physical or virtual
|
|
/// register. If Reg is physical, it must be a register unit (from
|
|
/// MCRegUnitIterator).
|
|
class PSetIterator {
|
|
const int *PSet = nullptr;
|
|
unsigned Weight = 0;
|
|
|
|
public:
|
|
PSetIterator() = default;
|
|
|
|
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
|
|
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
|
|
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
|
|
const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
|
|
PSet = TRI->getRegClassPressureSets(RC);
|
|
Weight = TRI->getRegClassWeight(RC).RegWeight;
|
|
}
|
|
else {
|
|
PSet = TRI->getRegUnitPressureSets(RegUnit);
|
|
Weight = TRI->getRegUnitWeight(RegUnit);
|
|
}
|
|
if (*PSet == -1)
|
|
PSet = nullptr;
|
|
}
|
|
|
|
bool isValid() const { return PSet; }
|
|
|
|
unsigned getWeight() const { return Weight; }
|
|
|
|
unsigned operator*() const { return *PSet; }
|
|
|
|
void operator++() {
|
|
assert(isValid() && "Invalid PSetIterator.");
|
|
++PSet;
|
|
if (*PSet == -1)
|
|
PSet = nullptr;
|
|
}
|
|
};
|
|
|
|
inline PSetIterator MachineRegisterInfo::
|
|
getPressureSets(unsigned RegUnit) const {
|
|
return PSetIterator(RegUnit, this);
|
|
}
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
|