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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 12:33:33 +02:00
llvm-mirror/test/CodeGen
Hal Finkel 7014e3d50f [PowerPC] Add support for dcbtst and icbt (prefetch)
Adds code generation support for dcbtst (data cache prefetch for write) and
icbt (instruction cache prefetch for read - Book E cores only).

We still end up with a 'cannot select' error for the non-supported prefetch
intrinsic forms. This will be fixed in a later commit.

Fixes PR20692.

llvm-svn: 216339
2014-08-23 23:21:04 +00:00
..
AArch64 [FastISel][AArch64] Add support for variable shift. 2014-08-21 23:06:07 +00:00
ARM Revert "ARM: improve RTABI 4.2 conformance on Linux" 2014-08-23 18:29:43 +00:00
CPP
Generic Use "weak alias" instead of "alias weak" 2014-07-30 22:51:54 +00:00
Hexagon DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range. 2014-08-06 00:21:25 +00:00
Inputs
Mips [mips] Don't use odd-numbered float registers for double arguments for fastcc 2014-08-22 09:23:22 +00:00
MSP430
NVPTX [NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types 2014-07-23 20:23:49 +00:00
PowerPC [PowerPC] Add support for dcbtst and icbt (prefetch) 2014-08-23 23:21:04 +00:00
R600 R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment 2014-08-22 18:49:35 +00:00
SPARC
SystemZ
Thumb ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
Thumb2 ARM / x86_64 varargs: Don't save regparms in prologue without va_start 2014-08-22 21:59:26 +00:00
X86 [x86] Start fixing a really subtle and terrible form of miscompile in 2014-08-23 10:25:15 +00:00
XCore