Kai Nacke fd99c3fbd8 [MIPS] Add cpu octeon and some instructions ... The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337		2014-03-20 11:51:58 +00:00
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Analysis	Add stride normalization to SCEV Normalize/Denormalize transformation.	2014-03-18 17:34:03 +00:00
AsmParser
Bitcode
CodeGen	Revert "Use the range machinery for DW_AT_ranges and DW_AT_high/lo_pc."	2014-03-20 00:12:06 +00:00
DebugInfo
ExecutionEngine
IR	Fix comment (PR19188)	2014-03-19 18:41:38 +00:00
IRReader
LineEditor
Linker
LTO
MC	Mark alias symbols as microMIPS if necessary. Differential Revision: http://llvm-reviews.chandlerc.com/D3080	2014-03-20 09:44:49 +00:00
Object	Object: Don't double-escape empty hexdata	2014-03-20 06:28:52 +00:00
Option
Support
TableGen
Target	[MIPS] Add cpu octeon and some instructions	2014-03-20 11:51:58 +00:00
Transforms	[ASan] Do not instrument globals from the llvm.metadata section.	2014-03-20 10:48:34 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile