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af453b57a3
This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
76 lines
2.3 KiB
ArmAsm
76 lines
2.3 KiB
ArmAsm
# RUN: llvm-mc -triple riscv32 -mattr=+c -riscv-no-aliases < %s -show-encoding \
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# RUN: | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
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# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
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# Check prefixes:
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# RELOC - Check the relocation in the object.
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# FIXUP - Check the fixup on the instruction.
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# INSTR - Check the instruction is handled properly by the ASMPrinter
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.long foo
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# RELOC: R_RISCV_32 foo
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.quad foo
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# RELOC: R_RISCV_64 foo
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lui t1, %hi(foo)
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# RELOC: R_RISCV_HI20 foo 0x0
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# INSTR: lui t1, %hi(foo)
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# FIXUP: fixup A - offset: 0, value: %hi(foo), kind: fixup_riscv_hi20
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lui t1, %hi(foo+4)
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# RELOC: R_RISCV_HI20 foo 0x4
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# INSTR: lui t1, %hi(foo+4)
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# FIXUP: fixup A - offset: 0, value: %hi(foo+4), kind: fixup_riscv_hi20
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addi t1, t1, %lo(foo)
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# RELOC: R_RISCV_LO12_I foo 0x0
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# INSTR: addi t1, t1, %lo(foo)
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# FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_i
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addi t1, t1, %lo(foo+4)
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# RELOC: R_RISCV_LO12_I foo 0x4
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# INSTR: addi t1, t1, %lo(foo+4)
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# FIXUP: fixup A - offset: 0, value: %lo(foo+4), kind: fixup_riscv_lo12_i
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sb t1, %lo(foo)(a2)
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# RELOC: R_RISCV_LO12_S foo 0x0
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# INSTR: sb t1, %lo(foo)(a2)
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# FIXUP: fixup A - offset: 0, value: %lo(foo), kind: fixup_riscv_lo12_s
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sb t1, %lo(foo+4)(a2)
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# RELOC: R_RISCV_LO12_S foo 0x4
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# INSTR: sb t1, %lo(foo+4)(a2)
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# FIXUP: fixup A - offset: 0, value: %lo(foo+4), kind: fixup_riscv_lo12_s
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auipc t1, %pcrel_hi(foo)
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# RELOC: R_RISCV_PCREL_HI20 foo 0x0
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# INSTR: auipc t1, %pcrel_hi(foo)
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# FIXUP: fixup A - offset: 0, value: %pcrel_hi(foo), kind: fixup_riscv_pcrel_hi20
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auipc t1, %pcrel_hi(foo+4)
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# RELOC: R_RISCV_PCREL_HI20 foo 0x4
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# INSTR: auipc t1, %pcrel_hi(foo+4)
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# FIXUP: fixup A - offset: 0, value: %pcrel_hi(foo+4), kind: fixup_riscv_pcrel_hi20
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jal zero, foo
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# RELOC: R_RISCV_JAL
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# INSTR: jal zero, foo
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_jal
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bgeu a0, a1, foo
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# RELOC: R_RISCV_BRANCH
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# INSTR: bgeu a0, a1, foo
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_branch
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c.jal foo
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# RELOC: R_RISCV_RVC_JUMP
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# INSTR: c.jal foo
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_jump
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c.bnez a0, foo
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# RELOC: R_RISCV_RVC_BRANCH
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# INSTR: c.bnez a0, foo
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# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_branch
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