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llvm-mirror/test/MC/RISCV/rv64i-pseudos.s
Kito Cheng dbc25360c6 [RISCV] Implement pseudo instructions for load/store from a symbol address.
Summary:
Those pseudo-instructions are making load/store instructions able to
load/store from/to a symbol, and its always using PC-relative addressing
to generating a symbol address.

Reviewers: asb, apazos, rogfer01, jrtc27

Differential Revision: https://reviews.llvm.org/D50496

llvm-svn: 354430
2019-02-20 03:31:32 +00:00

17 lines
421 B
ArmAsm

# RUN: llvm-mc %s -triple=riscv64 | FileCheck %s
# CHECK: .Lpcrel_hi0:
# CHECK: auipc a2, %pcrel_hi(a_symbol)
# CHECK: lwu a2, %pcrel_lo(.Lpcrel_hi0)(a2)
lwu a2, a_symbol
# CHECK: .Lpcrel_hi1:
# CHECK: auipc a3, %pcrel_hi(a_symbol)
# CHECK: ld a3, %pcrel_lo(.Lpcrel_hi1)(a3)
ld a3, a_symbol
# CHECK: .Lpcrel_hi2:
# CHECK: auipc a4, %pcrel_hi(a_symbol)
# CHECK: sd a3, %pcrel_lo(.Lpcrel_hi2)(a4)
sd a3, a_symbol, a4