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219b8c4930
Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
163 lines
6.9 KiB
TableGen
163 lines
6.9 KiB
TableGen
// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief WebAssembly Instruction definitions.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
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def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
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def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
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AssemblerPredicate<"FeatureSIMD128", "simd128">;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Node Types.
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//===----------------------------------------------------------------------===//
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def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
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def SDT_WebAssemblyCallSeqEnd :
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SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>;
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def SDT_WebAssemblyTableswitch : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>;
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def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>;
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def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
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SDTCisPtrTy<0>]>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def WebAssemblycallseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def WebAssemblycallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0",
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SDT_WebAssemblyCall0,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1",
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SDT_WebAssemblyCall1,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblytableswitch : SDNode<"WebAssemblyISD::TABLESWITCH",
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SDT_WebAssemblyTableswitch,
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[SDNPHasChain, SDNPVariadic]>;
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def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT",
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SDT_WebAssemblyArgument>;
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def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN",
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SDT_WebAssemblyReturn, [SDNPHasChain]>;
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def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper",
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SDT_WebAssemblyWrapper>;
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//===----------------------------------------------------------------------===//
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// WebAssembly-specific Operands.
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//===----------------------------------------------------------------------===//
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def bb_op : Operand<OtherVT>;
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def tjumptable_op : Operand<iPTR>;
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def global : Operand<iPTR>;
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format Definitions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Additional instructions.
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//===----------------------------------------------------------------------===//
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multiclass ARGUMENT<WebAssemblyRegClass vt> {
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let hasSideEffects = 1, Uses = [ARGUMENTS] in
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def ARGUMENT_#vt : I<(outs vt:$res), (ins i32imm:$argno),
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[(set vt:$res, (WebAssemblyargument timm:$argno))]>;
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}
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defm : ARGUMENT<I32>;
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defm : ARGUMENT<I64>;
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defm : ARGUMENT<F32>;
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defm : ARGUMENT<F64>;
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let Defs = [ARGUMENTS] in {
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// get_local and set_local are not generated by instruction selection; they
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// are implied by virtual register uses and defs in most contexts. However,
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// they are explicitly emitted for special purposes.
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multiclass LOCAL<WebAssemblyRegClass vt> {
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def GET_LOCAL_#vt : I<(outs vt:$res), (ins i32imm:$regno), [],
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"get_local\t$res, $regno">;
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// TODO: set_local returns its operand value
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def SET_LOCAL_#vt : I<(outs), (ins i32imm:$regno, vt:$src), [],
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"set_local\t$regno, $src">;
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// COPY_LOCAL is not an actual instruction in wasm, but since we allow
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// get_local and set_local to be implicit, we can have a COPY_LOCAL which
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// is actually a no-op because all the work is done in the implied
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// get_local and set_local.
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let isAsCheapAsAMove = 1 in
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def COPY_LOCAL_#vt : I<(outs vt:$res), (ins vt:$src), [],
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"copy_local\t$res, $src">;
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}
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defm : LOCAL<I32>;
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defm : LOCAL<I64>;
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defm : LOCAL<F32>;
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defm : LOCAL<F64>;
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def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
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[(set I32:$res, imm:$imm)],
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"i32.const\t$res, $imm">;
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def CONST_I64 : I<(outs I64:$res), (ins i64imm:$imm),
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[(set I64:$res, imm:$imm)],
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"i64.const\t$res, $imm">;
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def CONST_F32 : I<(outs F32:$res), (ins f32imm:$imm),
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[(set F32:$res, fpimm:$imm)],
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"f32.const\t$res, $imm">;
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def CONST_F64 : I<(outs F64:$res), (ins f64imm:$imm),
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[(set F64:$res, fpimm:$imm)],
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"f64.const\t$res, $imm">;
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} // Defs = [ARGUMENTS]
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def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$dst)),
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(CONST_I32 tglobaladdr:$dst)>;
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def : Pat<(i32 (WebAssemblywrapper texternalsym:$dst)),
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(CONST_I32 texternalsym:$dst)>;
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let Defs = [ARGUMENTS] in {
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def JUMP_TABLE : I<(outs I32:$dst), (ins tjumptable_op:$addr),
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[(set I32:$dst, (WebAssemblywrapper tjumptable:$addr))],
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"jump_table\t$dst, $addr">;
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// Function signature and local variable declaration "instructions".
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def PARAM : I<(outs), (ins variable_ops), [], ".param \t">;
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def RESULT : I<(outs), (ins variable_ops), [], ".result \t">;
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def LOCAL : I<(outs), (ins variable_ops), [], ".local \t">;
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} // Defs = [ARGUMENTS]
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//===----------------------------------------------------------------------===//
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// Additional sets of instructions.
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//===----------------------------------------------------------------------===//
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include "WebAssemblyInstrMemory.td"
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include "WebAssemblyInstrCall.td"
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include "WebAssemblyInstrControl.td"
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include "WebAssemblyInstrInteger.td"
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include "WebAssemblyInstrFloat.td"
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include "WebAssemblyInstrConv.td"
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include "WebAssemblyInstrAtomics.td"
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include "WebAssemblyInstrSIMD.td"
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