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219b8c4930
Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
156 lines
6.7 KiB
TableGen
156 lines
6.7 KiB
TableGen
// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief WebAssembly Memory operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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// TODO:
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// - HasAddr64
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// - WebAssemblyTargetLowering::isLegalAddressingMode
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// - WebAssemblyTargetLowering having to do with atomics
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// - Each has optional alignment and immediate byte offset.
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// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
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// local types. These memory-only types instead zero- or sign-extend into local
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// types when loading, and truncate when storing.
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let Defs = [ARGUMENTS] in {
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// Basic load.
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def LOAD_I32 : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (load I32:$addr))],
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"i32.load\t$dst, $addr">;
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def LOAD_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (load I32:$addr))],
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"i64.load\t$dst, $addr">;
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def LOAD_F32 : I<(outs F32:$dst), (ins I32:$addr),
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[(set F32:$dst, (load I32:$addr))],
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"f32.load\t$dst, $addr">;
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def LOAD_F64 : I<(outs F64:$dst), (ins I32:$addr),
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[(set F64:$dst, (load I32:$addr))],
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"f64.load\t$dst, $addr">;
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// Extending load.
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def LOAD8_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (sextloadi8 I32:$addr))],
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"i32.load8_s\t$dst, $addr">;
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def LOAD8_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (zextloadi8 I32:$addr))],
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"i32.load8_u\t$dst, $addr">;
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def LOAD16_S_I32 : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (sextloadi16 I32:$addr))],
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"i32.load16_s\t$dst, $addr">;
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def LOAD16_U_I32 : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (zextloadi16 I32:$addr))],
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"i32.load16_u\t$dst, $addr">;
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def LOAD8_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi8 I32:$addr))],
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"i64.load8_s\t$dst, $addr">;
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def LOAD8_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi8 I32:$addr))],
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"i64.load8_u\t$dst, $addr">;
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def LOAD16_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi16 I32:$addr))],
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"i64.load16_s\t$dst, $addr">;
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def LOAD16_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi16 I32:$addr))],
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"i64.load16_u\t$dst, $addr">;
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def LOAD32_S_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi32 I32:$addr))],
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"i64.load32_s\t$dst, $addr">;
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def LOAD32_U_I64 : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi32 I32:$addr))],
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"i64.load32_u\t$dst, $addr">;
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} // Defs = [ARGUMENTS]
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// "Don't care" extending load become zero-extending load.
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def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD8_U_I32 $addr)>;
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def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD16_U_I32 $addr)>;
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def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD8_U_I64 $addr)>;
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def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
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def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
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let Defs = [ARGUMENTS] in {
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// Basic store.
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// Note that we split the patterns out of the instruction definitions because
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// WebAssembly's stores return their operand value, and tablegen doesn't like
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// instruction definition patterns that don't reference all of the output
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// operands.
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// Note: WebAssembly inverts SelectionDAG's usual operand order.
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def STORE_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
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"i32.store\t$dst, $addr, $val">;
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def STORE_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
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"i64.store\t$dst, $addr, $val">;
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def STORE_F32 : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [],
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"f32.store\t$dst, $addr, $val">;
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def STORE_F64 : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [],
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"f64.store\t$dst, $addr, $val">;
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} // Defs = [ARGUMENTS]
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def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>;
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def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>;
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def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>;
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def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>;
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let Defs = [ARGUMENTS] in {
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// Truncating store.
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def STORE8_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
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"i32.store8\t$dst, $addr, $val">;
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def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
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"i32.store16\t$dst, $addr, $val">;
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def STORE8_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
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"i64.store8\t$dst, $addr, $val">;
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def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
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"i64.store16\t$dst, $addr, $val">;
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def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
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"i64.store32\t$dst, $addr, $val">;
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} // Defs = [ARGUMENTS]
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def : Pat<(truncstorei8 I32:$val, I32:$addr),
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(STORE8_I32 I32:$addr, I32:$val)>;
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def : Pat<(truncstorei16 I32:$val, I32:$addr),
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(STORE16_I32 I32:$addr, I32:$val)>;
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def : Pat<(truncstorei8 I64:$val, I32:$addr),
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(STORE8_I64 I32:$addr, I64:$val)>;
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def : Pat<(truncstorei16 I64:$val, I32:$addr),
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(STORE16_I64 I32:$addr, I64:$val)>;
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def : Pat<(truncstorei32 I64:$val, I32:$addr),
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(STORE32_I64 I32:$addr, I64:$val)>;
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let Defs = [ARGUMENTS] in {
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// Memory size.
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def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
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[(set I32:$dst, (int_wasm_memory_size))],
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"memory_size\t$dst">,
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Requires<[HasAddr32]>;
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def MEMORY_SIZE_I64 : I<(outs I64:$dst), (ins),
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[(set I64:$dst, (int_wasm_memory_size))],
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"memory_size\t$dst">,
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Requires<[HasAddr64]>;
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// Grow memory.
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def GROW_MEMORY_I32 : I<(outs), (ins I32:$delta),
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[(int_wasm_grow_memory I32:$delta)],
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"grow_memory\t$delta">,
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Requires<[HasAddr32]>;
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def GROW_MEMORY_I64 : I<(outs), (ins I64:$delta),
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[(int_wasm_grow_memory I64:$delta)],
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"grow_memory\t$delta">,
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Requires<[HasAddr64]>;
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} // Defs = [ARGUMENTS]
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