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https://github.com/RPCS3/llvm-mirror.git
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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
459 lines
22 KiB
LLVM
459 lines
22 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=SICI,PREGFX10
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefixes=VI,PREGFX10
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;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=GFX10
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;CHECK-LABEL: {{^}}buffer_load:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
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;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
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;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)
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%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)
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%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_dlc:
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;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
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;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
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;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
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;GFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc{{$}}
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;GFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc{{$}}
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;GFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
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%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
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%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 40, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
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;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4, i32 8188, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
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main_body:
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%ofs = add i32 %1, 60
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x1:
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;CHECK: buffer_load_dword v0, v0, s[0:3], 0 offen
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;CHECK: s_waitcnt
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define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %ofs) {
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main_body:
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%data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
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ret float %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x2:
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;CHECK: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen
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;CHECK: s_waitcnt
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define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %ofs) {
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main_body:
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%data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
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ret <2 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_negative_offset:
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;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
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;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0
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;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen
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define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
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main_body:
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%ofs.1 = add i32 %ofs, -16
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%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs.1, i32 0, i32 0)
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ret <4 x float> %data
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}
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; SI won't merge ds memory operations, because of the signed offset bug, so
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; we only have check lines for VI.
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; CHECK-LABEL: buffer_load_mmo:
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; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
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; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
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define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, float addrspace(3)* %lds) {
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entry:
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store float 0.0, float addrspace(3)* %lds
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%val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
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%tmp2 = getelementptr float, float addrspace(3)* %lds, i32 4
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store float 0.0, float addrspace(3)* %tmp2
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ret float %val
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
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%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
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%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
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%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
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main_body:
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%a = shl i32 %inp, 6
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%a1 = or i32 %a, 4
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%a2 = or i32 %a, 8
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%a3 = or i32 %a, 12
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%a4 = or i32 %a, 16
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%a5 = or i32 %a, 28
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%a6 = or i32 %a, 32
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%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 0)
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%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 0)
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%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 0)
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%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}}
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}}
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 8
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%a3 = add i32 %a, 12
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%a4 = add i32 %a, 16
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%a5 = add i32 %a, 28
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%a6 = add i32 %a, 32
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%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a3, i32 0, i32 1)
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%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a4, i32 0, i32 1)
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%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a5, i32 0, i32 3)
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%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %a6, i32 0, i32 3)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_and:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
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main_body:
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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%vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r1 = extractelement <2 x float> %vr1, i32 0
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%r2 = extractelement <2 x float> %vr1, i32 1
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%r3 = extractelement <2 x float> %vr2, i32 0
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%r4 = extractelement <2 x float> %vr2, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_or:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 4, v0
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
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main_body:
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%a = shl i32 %inp, 4
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%a1 = add i32 %a, 4
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%a2 = add i32 %a, 12
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%vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
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%vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
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%r1 = extractelement <2 x float> %vr1, i32 0
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%r2 = extractelement <2 x float> %vr1, i32 1
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%r3 = extractelement <2 x float> %vr2, i32 0
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%r4 = extractelement <2 x float> %vr2, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged:
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;CHECK-NEXT: %bb.
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;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
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;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28
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;CHECK: s_waitcnt
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define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
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main_body:
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%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
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%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
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%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
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%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0)
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%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
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%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
|
|
%vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
|
|
%r1 = extractelement <2 x float> %vr1, i32 0
|
|
%r2 = extractelement <2 x float> %vr1, i32 1
|
|
%r3 = extractelement <2 x float> %vr2, i32 0
|
|
%r4 = extractelement <2 x float> %vr2, i32 1
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}buffer_load_int:
|
|
;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
|
|
;CHECK: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
|
|
;CHECK: buffer_load_dword v6, off, s[0:3], 0 slc
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
|
|
main_body:
|
|
%data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0)
|
|
%data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1)
|
|
%data_slc = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %0, i32 0, i32 0, i32 2)
|
|
%fdata = bitcast <4 x i32> %data to <4 x float>
|
|
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
|
|
%fdata_slc = bitcast i32 %data_slc to float
|
|
%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
|
|
%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
|
|
%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
|
|
ret {<4 x float>, <2 x float>, float} %r2
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_ubyte:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_ubyte v{{[0-9]}}, off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
|
|
;CHECK-NEXT: ; return to shader part epilog
|
|
define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
%tmp2 = zext i8 %tmp to i32
|
|
%val = uitofp i32 %tmp2 to float
|
|
ret float %val
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_i16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_ushort v{{[0-9]}}, off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
;CHECK-NEXT: ; return to shader part epilog
|
|
define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
%tmp2 = zext i16 %tmp to i32
|
|
%val = uitofp i32 %tmp2 to float
|
|
ret float %val
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_sbyte:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_sbyte v{{[0-9]}}, off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
|
;CHECK-NEXT: ; return to shader part epilog
|
|
define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
%tmp2 = sext i8 %tmp to i32
|
|
%val = sitofp i32 %tmp2 to float
|
|
ret float %val
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_sshort:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_sshort v{{[0-9]}}, off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
|
|
;CHECK-NEXT: ; return to shader part epilog
|
|
define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
%tmp2 = sext i16 %tmp to i32
|
|
%val = sitofp i32 %tmp2 to float
|
|
ret float %val
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_f16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_ushort [[VAL:v[0-9]+]], off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK: ds_write_b16 v0, [[VAL]]
|
|
define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, half addrspace(3)* %ptr) {
|
|
main_body:
|
|
%val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
store half %val, half addrspace(3)* %ptr
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_v2f16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK: ds_write_b32 v0, [[VAL]]
|
|
define amdgpu_ps void @raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, <2 x half> addrspace(3)* %ptr) {
|
|
main_body:
|
|
%val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
store <2 x half> %val, <2 x half> addrspace(3)* %ptr
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_v4f16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK: ds_write_b64 v0, [[VAL]]
|
|
define amdgpu_ps void @raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, <4 x half> addrspace(3)* %ptr) {
|
|
main_body:
|
|
%val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
store <4 x half> %val, <4 x half> addrspace(3)* %ptr
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_v2i16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dword [[VAL:v[0-9]+]], off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK: ds_write_b32 v0, [[VAL]]
|
|
define amdgpu_ps void @raw_buffer_load_v2i16(<4 x i32> inreg %rsrc, <2 x i16> addrspace(3)* %ptr) {
|
|
main_body:
|
|
%val = call <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
store <2 x i16> %val, <2 x i16> addrspace(3)* %ptr
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_v4i16:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0
|
|
;CHECK: s_waitcnt vmcnt(0)
|
|
;CHECK: ds_write_b64 v0, [[VAL]]
|
|
define amdgpu_ps void @raw_buffer_load_v4i16(<4 x i32> inreg %rsrc, <4 x i16> addrspace(3)* %ptr) {
|
|
main_body:
|
|
%val = call <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
|
|
store <4 x i16> %val, <4 x i16> addrspace(3)* %ptr
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_merged:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dwordx4 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
|
|
;CHECK-NEXT: buffer_load_dwordx2 v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
|
|
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
|
|
%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
|
|
%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 0)
|
|
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 0)
|
|
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 0)
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
|
|
ret void
|
|
}
|
|
|
|
;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_swizzled_not_merged:
|
|
;CHECK-NEXT: %bb.
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:4
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:8
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:12
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:16
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:28
|
|
;CHECK-NEXT: buffer_load_dword v{{[0-9]}}, off, s[0:3], 0 offset:32
|
|
;CHECK: s_waitcnt
|
|
define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc) {
|
|
main_body:
|
|
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8)
|
|
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 8)
|
|
%r3 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 12, i32 0, i32 8)
|
|
%r4 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 16, i32 0, i32 8)
|
|
%r5 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 28, i32 0, i32 8)
|
|
%r6 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 32, i32 0, i32 8)
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r1, float %r2, float %r3, float %r4, i1 true, i1 true)
|
|
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %r5, float %r6, float undef, float undef, i1 true, i1 true)
|
|
ret void
|
|
}
|
|
|
|
declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #0
|
|
declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #0
|
|
declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #0
|
|
declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32) #0
|
|
declare <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32>, i32, i32, i32) #0
|
|
declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #0
|
|
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
|
declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #0
|
|
declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32) #0
|
|
declare <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32>, i32, i32, i32) #0
|
|
declare <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32>, i32, i32, i32) #0
|
|
declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0
|
|
declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0
|
|
declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0
|
|
|
|
attributes #0 = { nounwind readonly }
|