Victor Campos 14293748bd [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator ... Summary: In TableGen's instruction selection table generator, references to register classes were handled by generating a matcher table entry in the form of "EmitStringInteger, MVT::i32, 'RegisterClassID'". This ID is in fact the enum integer value corresponding to the register class. However, both the table generator and the table consumer (SelectionDAGISel) assume that this ID is less than or equal to 127, i.e. at most 7 bits. Values greater than this threshold cause completely wrong behaviours in the instruction selection process. This patch adds a check to determine if the enum integer value is greater than the limit of 127. In finding so, the generator emits an "EmitInteger" instead, which properly supports values with arbitrary sizes. Commit f8d044bbcfdc9e1ddc02247ffb86fe39e1f277f0 fixed the very same bug for register subindices. The present patch now extends this cover to register classes. Reviewers: rampitec Reviewed By: rampitec Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79705		2020-05-13 10:17:03 +01:00
..
Common	[TBLGEN] Emit register pressure set enum	2020-02-18 10:09:05 -08:00
FixedLenDecoderEmitter
GICombinerEmitter	[gicombiner] Correct 64f1bb5cd2c to account for MSVC's %p format	2020-01-07 12:50:05 -08:00
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
address-space-patfrags.td	[Alignment][NFC] Transitionning more getMachineMemOperand call sites	2020-03-31 08:36:18 +00:00
AllowDuplicateRegisterNames.td
ambiguous-composition.td
AnonDefinitionOnDemand.td
arithmetic.td
AsmPredicateCombining.td	[TableGen] Support combining AssemblerPredicates with ORs	2020-03-13 17:13:51 +00:00
AsmPredicateCombiningRISCV.td	[TableGen] Support combining AssemblerPredicates with ORs	2020-03-13 17:13:51 +00:00
AsmPredicateCondsEmission.td	[TableGen] Support combining AssemblerPredicates with ORs	2020-03-13 17:13:51 +00:00
AsmVariant.td
BigEncoder.td
BitOffsetDecoder.td
BitsInit.td	[TableGen] Fix spurious type error in bit assignment.	2020-02-07 15:11:42 +00:00
BitsInitOverflow.td
cast-list-initializer.td
cast-multiclass.td
cast-typeerror.td
cast.td
ClassInstanceValue.td
code.td
compare.td
ConcatenatedSubregs.td	[llvm] NFC: Fix trivial typo in rst and td files	2020-04-23 14:26:32 +09:00
cond-bitlist.td
cond-default.td
cond-empty-list-arg.td
cond-inheritance.td
cond-let.td
cond-list.td
cond-subclass.td
cond-type.td
cond-usage.td
condsbit.td
ConstraintChecking1.td
ConstraintChecking2.td
ConstraintChecking3.td
ConstraintChecking4.td
ConstraintChecking5.td
ConstraintChecking6.td
ConstraintChecking7.td
ConstraintChecking.inc
CStyleComment.td
dag-functional.td
dag-isel-regclass-emit-enum.td	[TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator	2020-05-13 10:17:03 +01:00
dag-isel-res-order.td
dag-isel-subregs.td	[TBLGEN] Fix subreg value overflow in DAGISelMatcher	2020-02-12 13:29:57 -08:00
Dag.td
DAGDefaultOps.td
DefaultOpsGlobalISel.td	TableGen: Fix logic for default operands	2020-02-19 23:41:07 -05:00
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
defset-typeerror.td
defset.td
defvar.td	[TableGen] Introduce an if/then/else statement.	2020-01-14 10:19:53 +00:00
duplicate-include.inc
duplicate-include.td
DuplicateFieldValues.td
eq-unset.td	Fix assertion on !eq(?, 0)	2020-02-18 14:05:55 -08:00
eq.td
eqbit.td
FastISelEmitter.td
field-access-initializers.td	[llvm][TableGen] Define FieldInit::isConcrete overload	2020-02-10 18:04:58 -08:00
FieldAccess.td
foldl.td
foreach-eval.td
foreach-leak.td
foreach-multiclass.td
foreach-range-parse-errors0.td
foreach-range-parse-errors1.td
foreach-range-parse-errors2.td
foreach-range-parse-errors3.td
foreach-range-parse-errors4.td
foreach-range-parse-errors5.td
foreach-variable-range.td
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
generic-tables-instruction.td
generic-tables.td	[TableGen] Diagnose undefined fields when generating searchable tables	2020-02-19 14:03:48 +00:00
get-operand-type.td
getsetop.td
gisel-physreg-input.td
GlobalISelEmitter-immarg-literal-pattern.td	TableGen/GlobalISel: Fix pattern matching of immarg literals	2020-01-09 17:37:52 -05:00
GlobalISelEmitter-input-discard.td	TableGen/GlobalISel: Don't check exact intrinsic opcode value	2020-01-17 20:09:53 -05:00
GlobalISelEmitter-PR39045.td
GlobalISelEmitter-SDNodeXForm-timm.td	TableGen/GlobalISel: Add way for SDNodeXForm to work on timm	2020-01-09 17:37:52 -05:00
GlobalISelEmitter-setcc.td
GlobalISelEmitter.td	TableGen/GlobalISel: Add way for SDNodeXForm to work on timm	2020-01-09 17:37:52 -05:00
GlobalISelEmitterOverloadedPtr.td
GlobalISelEmitterRegSequence.td	TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands	2020-04-14 22:05:22 -04:00
GlobalISelEmitterSkippedPatterns.td
GlobalISelEmitterSubreg.td	TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG	2020-01-24 12:15:10 -08:00
GlobalISelEmitterVariadic.td
HwModeEncodeDecode.td
HwModeSelect.td	Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""	2020-02-13 10:16:06 -08:00
if-empty-list-arg.td
if-type.td
if.td
ifbit.td
ifstmt.td	[TableGen] Introduce an if/then/else statement.	2020-01-14 10:19:53 +00:00
immarg.td
Include.inc
Include.td
inhibit-pset.td	[TBLGEN] Inhibit generation of unneeded psets	2020-02-17 15:38:08 -08:00
IntBitInit.td
intrin-side-effects.td
intrinsic-long-name.td	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
intrinsic-pointer-to-any.td
intrinsic-struct.td	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
intrinsic-varargs.td
IntSpecialValues.td
InvalidMCSchedClassDesc.td
isa.td
JSON-check.py
JSON.td
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
listpaste.td
ListSlices.td
listsplat.td
lit.local.cfg
LoLoL.td
math.td
MultiClass-def-fail.td
MultiClass-defm-fail.td
MultiClass-defm.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
name-resolution-consistency.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
predicate-patfags.td	TableGen: Fix assert on PatFrags with predicate code	2019-12-30 14:24:25 -05:00
prep-diag1.td
prep-diag2.td
prep-diag3.td
prep-diag4.td
prep-diag5.td
prep-diag6.td
prep-diag7.td
prep-diag8.td
prep-diag9.td
prep-diag10.td
prep-diag11-include.inc
prep-diag11.td
prep-diag12-include.inc
prep-diag12.td
prep-diag13.td
prep-diag14.td
prep-ifndef-diag-1.td
prep-ifndef-diag-2.td
prep-ifndef.td
prep-region-include.inc
prep-region-processing.td	[llvm] NFC: Fix trivial typo in rst and td files	2020-04-23 14:26:32 +09:00
pset-enum.td	[TBLGEN] Emit register pressure set enum	2020-02-18 10:09:05 -08:00
rc-weight-override.td	[TBLGEN] Allow to override RC weight	2020-02-14 15:49:52 -08:00
RegisterBankEmitter.td
RegisterEncoder.td
RelTest.td
SchedModelError.td
searchabletables-intrinsic.td
self-reference-recursion.td
self-reference-typeerror.td
self-reference.td
SetTheory.td
SiblingForeach.td
simplify-patfrag.td	[TableGen] Don't elide bitconverts in PatFrag fragments.	2020-02-17 09:30:45 +00:00
size.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
template-arg-dependency.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td
trydecode-emission3.td
trydecode-emission.td
TwoLevelName.td
UnsetBitInit.td
unsetop.td
unterminated-c-comment-include.inc
unterminated-c-comment.td
unterminated-code-block-include.inc
unterminated-code-block.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td