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70 lines
2.3 KiB
TableGen
70 lines
2.3 KiB
TableGen
//=-LanaiSchedule.td - Lanai Scheduling Definitions --*- tablegen -*-=========//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def ALU_FU : FuncUnit;
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def LDST_FU : FuncUnit;
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def IIC_ALU : InstrItinClass;
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def IIC_LD : InstrItinClass;
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def IIC_ST : InstrItinClass;
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def IIC_LDSW : InstrItinClass;
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def IIC_STSW : InstrItinClass;
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def LanaiItinerary : ProcessorItineraries<[ALU_FU, LDST_FU],[],[
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InstrItinData<IIC_LD, [InstrStage<1, [LDST_FU]>]>,
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InstrItinData<IIC_ST, [InstrStage<1, [LDST_FU]>]>,
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InstrItinData<IIC_LDSW, [InstrStage<2, [LDST_FU]>]>,
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InstrItinData<IIC_STSW, [InstrStage<2, [LDST_FU]>]>,
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InstrItinData<IIC_ALU, [InstrStage<1, [ALU_FU]>]>
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]>;
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def LanaiSchedModel : SchedMachineModel {
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// Cycles for loads to access the cache [default = -1]
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let LoadLatency = 2;
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// Max micro-ops that can be buffered for optimized loop dispatch/execution.
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// [default = -1]
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let LoopMicroOpBufferSize = 0;
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// Allow scheduler to assign default model to any unrecognized opcodes.
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// [default = 1]
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let CompleteModel = 0;
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// Max micro-ops that may be scheduled per cycle. [default = 1]
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let IssueWidth = 1;
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// Extra cycles for a mispredicted branch. [default = -1]
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let MispredictPenalty = 10;
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// Enable Post RegAlloc Scheduler pass. [default = 0]
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let PostRAScheduler = 0;
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// Max micro-ops that can be buffered. [default = -1]
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let MicroOpBufferSize = 0;
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// Per-cycle resources tables. [default = NoItineraries]
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let Itineraries = LanaiItinerary;
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}
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def ALU : ProcResource<1> { let BufferSize = 0; }
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def LdSt : ProcResource<1> { let BufferSize = 0; }
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def WriteLD : SchedWrite;
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def WriteST : SchedWrite;
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def WriteLDSW : SchedWrite;
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def WriteSTSW : SchedWrite;
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def WriteALU : SchedWrite;
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let SchedModel = LanaiSchedModel in {
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def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
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def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
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def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
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def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }
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}
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