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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
52 lines
2.1 KiB
LLVM
52 lines
2.1 KiB
LLVM
; RUN: llc -O0 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10"
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; This file contains functions that may crash llc -O0
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; The DIV8 instruction produces results in AH and AL, but we don't want to use
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; AH in 64-bit mode. The hack used must not generate copyFromReg nodes for
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; aliased registers (AX and AL) - RegAllocFast does not like that.
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; PR7312
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define i32 @div8() nounwind {
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entry:
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%0 = trunc i64 undef to i8 ; <i8> [#uses=3]
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%1 = udiv i8 0, %0 ; <i8> [#uses=1]
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%2 = urem i8 0, %0 ; <i8> [#uses=1]
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%3 = icmp uge i8 %2, %0 ; <i1> [#uses=1]
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br i1 %3, label %"40", label %"39"
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"39": ; preds = %"36"
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%4 = zext i8 %1 to i32 ; <i32> [#uses=1]
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%5 = mul nsw i32 %4, undef ; <i32> [#uses=1]
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%6 = add nsw i32 %5, undef ; <i32> [#uses=1]
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%7 = icmp ne i32 %6, undef ; <i1> [#uses=1]
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br i1 %7, label %"40", label %"41"
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"40": ; preds = %"39", %"36"
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unreachable
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"41": ; preds = %"39"
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unreachable
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}
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; When using fast isel, sdiv is lowered into a sequence of CQO + DIV64.
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; CQO defines implicitly AX and DIV64 uses it implicitly too.
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; When an instruction gets between those two, RegAllocFast was reusing
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; AX for the vreg defined in between and the compiler crashed.
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;
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; An instruction gets between CQO and DIV64 because the load is folded
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; into the division but it requires a sign extension.
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; PR21700
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; CHECK-LABEL: addressModeWith32bitIndex:
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; CHECK: cqto
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; CHECK-NEXT: movslq
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; CHECK-NEXT: idivq
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; CHECK: retq
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define i64 @addressModeWith32bitIndex(i32 %V) {
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%gep = getelementptr i64, i64* null, i32 %V
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%load = load i64, i64* %gep
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%sdiv = sdiv i64 0, %load
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ret i64 %sdiv
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}
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