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48 lines
1.8 KiB
TableGen
48 lines
1.8 KiB
TableGen
//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the AMD Secure Nested
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// Paging (SNP) instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SNP instructions
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let SchedRW = [WriteSystem] in {
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// F3 0F 01 FF
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let Uses = [RAX] in
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def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, XS,
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Requires<[In64BitMode]>;
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// F2 0F 01 FF
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let Uses = [RAX] in
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def PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
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XD, Requires<[In64BitMode]>;
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let Uses = [EAX] in
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def PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
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XD, Requires<[Not64BitMode]>;
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// F2 0F 01 FE
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let Uses = [RAX] in
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def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD,
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Requires<[In64BitMode]>;
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// F3 0F 01 FE
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let Uses = [RAX] in
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def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, XS,
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Requires<[In64BitMode]>;
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} // SchedRW
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def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
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def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
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def : InstAlias<"pvalidate\t{%eax|eax}", (PVALIDATE32)>, Requires<[Not64BitMode]>;
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def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
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def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;
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