..
AArch64
[AArch64]Merge halfword loads into a 32-bit load
2015-10-27 19:16:03 +00:00
AMDGPU
AMDGPU/SI: handle undef for llvm.SI.packf16
2015-10-29 15:29:09 +00:00
ARM
ARM: add support for WatchOS's compact unwind information.
2015-10-28 22:56:36 +00:00
BPF
[bpf] Do not expand UNDEF SDNode during insn selection lowering
2015-10-08 18:52:40 +00:00
CPP
Generic
Revert "[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll"
2015-10-29 22:34:59 +00:00
Hexagon
Tail duplication can mix incompatible registers in phi nodes
2015-10-21 02:40:06 +00:00
Inputs
Mips
[mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used
2015-10-29 14:40:19 +00:00
MIR
Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add successors when optimization is disabled.
2015-10-27 17:59:36 +00:00
MSP430
NVPTX
PowerPC
[PowerPC] Recurse through constants when looking for TLS globals
2015-10-28 23:43:00 +00:00
SPARC
Drop assert that a call with struct return goes to a function with sret
2015-10-21 20:05:01 +00:00
SystemZ
[SystemZ] Make the CCRegs regclass non-allocatable.
2015-10-29 16:13:55 +00:00
Thumb
[ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.
2015-10-05 14:49:54 +00:00
Thumb2
[ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev
2015-10-23 17:19:19 +00:00
WebAssembly
[WebAssembly] Update opcode name format for conversions
2015-10-29 04:10:52 +00:00
WinEH
[WinEH] Fix eh.exceptionpointer intrinsic lowering
2015-10-17 00:08:08 +00:00
X86
[X86][SSE] Added load+sext tests for 16i1->16i8 and 32i1->32i8
2015-10-29 22:19:21 +00:00
XCore