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Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. llvm-svn: 167699 |
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.. | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
cl_common_defines.h | ||
CMakeLists.txt | ||
gen-register-defs.py | ||
LLVMBuild.txt | ||
Makefile | ||
ManagedStringPool.h | ||
NVPTX.h | ||
NVPTX.td | ||
NVPTXAllocaHoisting.cpp | ||
NVPTXAllocaHoisting.h | ||
NVPTXAsmPrinter.cpp | ||
NVPTXAsmPrinter.h | ||
NVPTXFrameLowering.cpp | ||
NVPTXFrameLowering.h | ||
NVPTXInstrFormats.td | ||
NVPTXInstrInfo.cpp | ||
NVPTXInstrInfo.h | ||
NVPTXInstrInfo.td | ||
NVPTXIntrinsics.td | ||
NVPTXISelDAGToDAG.cpp | ||
NVPTXISelDAGToDAG.h | ||
NVPTXISelLowering.cpp | ||
NVPTXISelLowering.h | ||
NVPTXLowerAggrCopies.cpp | ||
NVPTXLowerAggrCopies.h | ||
NVPTXNumRegisters.h | ||
NVPTXRegisterInfo.cpp | ||
NVPTXRegisterInfo.h | ||
NVPTXRegisterInfo.td | ||
NVPTXSection.h | ||
NVPTXSplitBBatBar.cpp | ||
NVPTXSplitBBatBar.h | ||
NVPTXSubtarget.cpp | ||
NVPTXSubtarget.h | ||
NVPTXTargetMachine.cpp | ||
NVPTXTargetMachine.h | ||
NVPTXTargetObjectFile.h | ||
NVPTXutil.cpp | ||
NVPTXutil.h | ||
NVPTXUtilities.cpp | ||
NVPTXUtilities.h | ||
NVPTXVector.td | ||
VectorElementize.cpp |