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https://github.com/RPCS3/llvm-mirror.git
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6f47a197aa
Summary: Allow Mips fast-isel to handle functions which return i8/i16 signed/unsigned. Test Plan: Make check tests are forthcoming. Already passes test-suite at O0/O2 for Mips 32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6765 llvm-svn: 236103
109 lines
3.6 KiB
LLVM
109 lines
3.6 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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@i = global i32 75, align 4
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@s = global i16 -345, align 2
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@c = global i8 118, align 1
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@f = global float 0x40BE623360000000, align 4
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@d = global double 1.298330e+03, align 8
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; Function Attrs: nounwind
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define i32 @reti() {
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entry:
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; CHECK-LABEL: reti:
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%0 = load i32, i32* @i, align 4
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ret i32 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_I_ADDR:[0-9]+]], %got(i)($[[REG_GP]])
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; CHECK: lw $2, 0($[[REG_I_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define i16 @retus() {
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entry:
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; CHECK-LABEL: retus:
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%0 = load i16, i16* @s, align 2
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ret i16 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])
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; CHECK: lhu $2, 0($[[REG_S_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define signext i16 @rets() {
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entry:
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; CHECK-LABEL: rets:
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%0 = load i16, i16* @s, align 2
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ret i16 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_S_ADDR:[0-9]+]], %got(s)($[[REG_GP]])
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; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])
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; CHECK: seh $2, $[[REG_S]]
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define i8 @retuc() {
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entry:
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; CHECK-LABEL: retuc:
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%0 = load i8, i8* @c, align 1
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ret i8 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])
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; CHECK: lbu $2, 0($[[REG_C_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define signext i8 @retc() {
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entry:
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; CHECK-LABEL: retc:
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%0 = load i8, i8* @c, align 1
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ret i8 %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_C_ADDR:[0-9]+]], %got(c)($[[REG_GP]])
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; CHECK: lbu $[[REG_C:[0-9]+]], 0($[[REG_C_ADDR]])
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; CHECK: seb $2, $[[REG_C]]
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define float @retf() {
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entry:
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; CHECK-LABEL: retf:
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%0 = load float, float* @f, align 4
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ret float %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_F_ADDR:[0-9]+]], %got(f)($[[REG_GP]])
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; CHECK: lwc1 $f0, 0($[[REG_F_ADDR]])
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; CHECK: jr $ra
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}
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; Function Attrs: nounwind
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define double @retd() {
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entry:
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; CHECK-LABEL: retd:
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%0 = load double, double* @d, align 8
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ret double %0
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; CHECK: lui $[[REG_GPa:[0-9]+]], %hi(_gp_disp)
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; CHECK: addiu $[[REG_GPb:[0-9]+]], $[[REG_GPa]], %lo(_gp_disp)
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; CHECK: addu $[[REG_GP:[0-9]+]], $[[REG_GPb]], $25
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; CHECK: lw $[[REG_D_ADDR:[0-9]+]], %got(d)($[[REG_GP]])
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; CHECK: ldc1 $f0, 0($[[REG_D_ADDR]])
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; CHECK: jr $ra
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}
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