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95d8094810
The _Int instructions are special, in that they operate on the full
VR128 instead of FR32. The load folding then looks at MOVSS, at the
user, and bails out when it sees a size mismatch.
What we really know is that the rm_Int instructions don't load the
higher lanes, so folding is fine.
This happens for the straightforward intrinsic code, e.g.:
_mm_add_ss(a, _mm_load_ss(p));
Fixes PR23349.
Differential Revision: http://reviews.llvm.org/D10554
llvm-svn: 240326
143 lines
3.9 KiB
LLVM
143 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse2 < %s | FileCheck %s --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s --check-prefix=AVX
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; Verify that we're folding the load into the math instruction.
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; This pattern is generated out of the simplest intrinsics usage:
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; _mm_add_ss(a, _mm_load_ss(b));
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define <4 x float> @addss(<4 x float> %va, float* %pb) {
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; SSE-LABEL: addss:
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; SSE: # BB#0:
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; SSE-NEXT: addss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: addss:
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; AVX: # BB#0:
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; AVX-NEXT: vaddss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <4 x float> %va, i32 0
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%b = load float, float* %pb
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%r = fadd float %a, %b
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%vr = insertelement <4 x float> %va, float %r, i32 0
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ret <4 x float> %vr
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}
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define <2 x double> @addsd(<2 x double> %va, double* %pb) {
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; SSE-LABEL: addsd:
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; SSE: # BB#0:
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; SSE-NEXT: addsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: addsd:
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; AVX: # BB#0:
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; AVX-NEXT: vaddsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <2 x double> %va, i32 0
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%b = load double, double* %pb
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%r = fadd double %a, %b
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%vr = insertelement <2 x double> %va, double %r, i32 0
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ret <2 x double> %vr
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}
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define <4 x float> @subss(<4 x float> %va, float* %pb) {
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; SSE-LABEL: subss:
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; SSE: # BB#0:
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; SSE-NEXT: subss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: subss:
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; AVX: # BB#0:
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; AVX-NEXT: vsubss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <4 x float> %va, i32 0
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%b = load float, float* %pb
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%r = fsub float %a, %b
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%vr = insertelement <4 x float> %va, float %r, i32 0
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ret <4 x float> %vr
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}
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define <2 x double> @subsd(<2 x double> %va, double* %pb) {
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; SSE-LABEL: subsd:
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; SSE: # BB#0:
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; SSE-NEXT: subsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: subsd:
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; AVX: # BB#0:
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; AVX-NEXT: vsubsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <2 x double> %va, i32 0
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%b = load double, double* %pb
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%r = fsub double %a, %b
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%vr = insertelement <2 x double> %va, double %r, i32 0
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ret <2 x double> %vr
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}
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define <4 x float> @mulss(<4 x float> %va, float* %pb) {
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; SSE-LABEL: mulss:
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; SSE: # BB#0:
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; SSE-NEXT: mulss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: mulss:
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; AVX: # BB#0:
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; AVX-NEXT: vmulss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <4 x float> %va, i32 0
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%b = load float, float* %pb
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%r = fmul float %a, %b
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%vr = insertelement <4 x float> %va, float %r, i32 0
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ret <4 x float> %vr
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}
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define <2 x double> @mulsd(<2 x double> %va, double* %pb) {
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; SSE-LABEL: mulsd:
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; SSE: # BB#0:
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; SSE-NEXT: mulsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: mulsd:
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; AVX: # BB#0:
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; AVX-NEXT: vmulsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <2 x double> %va, i32 0
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%b = load double, double* %pb
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%r = fmul double %a, %b
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%vr = insertelement <2 x double> %va, double %r, i32 0
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ret <2 x double> %vr
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}
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define <4 x float> @divss(<4 x float> %va, float* %pb) {
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; SSE-LABEL: divss:
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; SSE: # BB#0:
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; SSE-NEXT: divss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: divss:
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; AVX: # BB#0:
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; AVX-NEXT: vdivss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <4 x float> %va, i32 0
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%b = load float, float* %pb
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%r = fdiv float %a, %b
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%vr = insertelement <4 x float> %va, float %r, i32 0
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ret <4 x float> %vr
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}
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define <2 x double> @divsd(<2 x double> %va, double* %pb) {
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; SSE-LABEL: divsd:
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; SSE: # BB#0:
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; SSE-NEXT: divsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: divsd:
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; AVX: # BB#0:
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; AVX-NEXT: vdivsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%a = extractelement <2 x double> %va, i32 0
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%b = load double, double* %pb
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%r = fdiv double %a, %b
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%vr = insertelement <2 x double> %va, double %r, i32 0
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ret <2 x double> %vr
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}
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