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f83e7bf498
Summary: Some constants can be handled with less instructions than our current results. And it seems our original approach is not very easy to extend. Therefore this patch proposes to materialize all 64-bit constants by enumerated patterns. I traversed almost all constants to verified the functionality of these pattens. A traversed comparison of the number of instructions used by the original method and the new method has also been completed, where no degradation was caused by this patch. This patch also passed Bootstrap test and SPEC test. Improvements of this patch are shown in llvm/test/CodeGen/PowerPC/constants-i64.ll Reviewed By: steven.zhang, stefanp Differential Revision: https://reviews.llvm.org/D92089
90 lines
3.0 KiB
LLVM
90 lines
3.0 KiB
LLVM
; RUN: llc < %s -mcpu=a2 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mcpu=a2 -disable-lsr -verify-machineinstrs | FileCheck -check-prefix=NOLSR %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @main() #0 {
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entry:
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br i1 undef, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 0
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br i1 %exitcond, label %for.end, label %for.body
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; CHECK: @main
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; CHECK: li [[REG:[0-9]+]], -1
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; CHECK: rldic [[REG2:[0-9]+]], [[REG]], 0, 32
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; CHECK: mtctr [[REG2]]
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; CHECK: bdnz
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for.end: ; preds = %for.body, %entry
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ret void
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}
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define void @main1() #0 {
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entry:
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br i1 undef, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
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%indvars.iv.next = add i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 0
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br i1 %exitcond, label %for.end, label %for.body
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; FIXME: This should be a hardware loop.
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; cmp is optimized to uadd intrinsic in CGP pass which can not be recognized in
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; later HardwareLoops Pass.
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; CHECK: @main1
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; CHECK: li [[REG:[0-9]+]], 1
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; CHECK: addi [[REG2:[0-9]+]], [[REG]], 1
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; CHECK: cmpld
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; CHECK: bge
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for.end: ; preds = %for.body, %entry
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ret void
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}
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define void @main2() #0 {
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entry:
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br i1 undef, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 1, %entry ]
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%indvars.iv.next = add i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, -100000
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br i1 %exitcond, label %for.end, label %for.body
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; CHECK: @main2
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; CHECK: lis [[REG:[0-9]+]], -2
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; CHECK: ori [[REG2:[0-9]+]], [[REG]], 31071
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; CHECK: mtctr [[REG2]]
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; CHECK: bdnz
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for.end: ; preds = %for.body, %entry
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ret void
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}
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define void @main3() #0 {
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entry:
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br i1 undef, label %for.end, label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 127984, %entry ]
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%indvars.iv.next = add i64 %indvars.iv, -16
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%exitcond = icmp eq i64 %indvars.iv.next, -16
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br i1 %exitcond, label %for.end, label %for.body
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; NOLSR: @main3
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; NOLSR: li [[REG:[0-9]+]], 8000
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; NOLSR: mtctr [[REG]]
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; NOLSR: bdnz
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for.end: ; preds = %for.body, %entry
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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