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9cab004124
Current powerpc64le backend hits ``` Combining: t7: f64 = uint_to_fp t6 llc: llvm-project/llvm/include/llvm/CodeGen/ValueTypes.h:291: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed. ``` This patch fixes it by skipping combination if `t6` is not simple type. Fixed https://bugs.llvm.org/show_bug.cgi?id=47660. Reviewed By: #powerpc, steven.zhang Differential Revision: https://reviews.llvm.org/D88388
46 lines
1.6 KiB
LLVM
46 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-LE %s
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-BE %s
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define dso_local i24 @_Z1f1c(i24 %g.coerce) local_unnamed_addr #0 {
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; CHECK-LE-LABEL: _Z1f1c:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: clrlwi r3, r3, 24
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; CHECK-LE-NEXT: xxlxor f1, f1, f1
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; CHECK-LE-NEXT: mtfprwz f0, r3
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; CHECK-LE-NEXT: xscvuxddp f0, f0
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; CHECK-LE-NEXT: xsmuldp f0, f0, f1
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; CHECK-LE-NEXT: xscvdpsxws f0, f0
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; CHECK-LE-NEXT: mffprwz r3, f0
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; CHECK-LE-NEXT: clrldi r3, r3, 32
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: _Z1f1c:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: clrldi r3, r3, 56
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; CHECK-BE-NEXT: std r3, -16(r1)
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; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-BE-NEXT: lfd f0, -16(r1)
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; CHECK-BE-NEXT: lfs f1, .LCPI0_0@toc@l(r3)
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; CHECK-BE-NEXT: fcfid f0, f0
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; CHECK-BE-NEXT: fmul f0, f0, f1
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; CHECK-BE-NEXT: fctiwz f0, f0
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; CHECK-BE-NEXT: stfd f0, -8(r1)
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; CHECK-BE-NEXT: lwz r3, -4(r1)
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; CHECK-BE-NEXT: clrldi r3, r3, 32
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; CHECK-BE-NEXT: blr
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entry:
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%0 = and i24 %g.coerce, 255
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%conv1 = uitofp i24 %0 to double
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%mul = fmul double 0.000000e+00, %conv1
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%conv2 = fptoui double %mul to i8
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%retval.sroa.0.0.insert.ext = zext i8 %conv2 to i24
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ret i24 %retval.sroa.0.0.insert.ext
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}
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attributes #0 = { "use-soft-float"="false" }
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