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Mirror of https://github.com/RPCS3/llvm-mirror
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Sjoerd Meijer db5ee9a2c0 [ARM] Allow half types in ConstantPool 
Change ARMConstantIslandPass to:
- accept f16 literals as litpool entries,
- if the litpool needs to be inserted in the middle of a big block, then we
  need to 4-byte align the next instruction in ARM mode.

Differential Revision: https://reviews.llvm.org/D42784

llvm-svn: 325012
2018-02-13 15:34:09 +00:00
bindings [NFC] fix trivial typos in comments and documents 2018-01-26 08:15:29 +00:00
cmake Generate PDB files for profiling even in Release build. 2018-02-07 19:37:52 +00:00
docs Reapply "AMDGPU: Add 32-bit constant address space" 2018-02-09 16:57:57 +00:00
examples [ORC] Remove Layer handles from the layer concept. 2018-02-09 02:30:40 +00:00
include Revert "Rewrite the cached map used for locating the most precise DIE among inlined subroutines for a given address." 2018-02-13 01:52:30 +00:00
lib [ARM] Allow half types in ConstantPool 2018-02-13 15:34:09 +00:00
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test [ARM] Allow half types in ConstantPool 2018-02-13 15:34:09 +00:00
tools [llvm-objcopy] Make modifications in-place if output is not specified 2018-02-09 23:33:31 +00:00
unittests [WebAssembly] Update ADT/TripleTest.cpp now that default file format has changed 2018-02-12 23:47:38 +00:00
utils [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
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CMakeLists.txt CMake: Allow specifying arbitrary CCACHE parameters 2018-02-09 23:25:23 +00:00
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CREDITS.TXT Add myself to CREDITS.txt 2018-01-29 17:02:34 +00:00
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README.txt 

Low Level Virtual Machine (LLVM)
================================

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Please see the documentation provided in docs/ for further
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